For the past 45 years, relentless focus on Moore’s Law transistor scaling has provided ever-increasing CMOS transistor performance and density. For much of this time, Moore’s Law transistor scaling meant “classic” Dennard scaling (1). However, in recent years, Dennard scaling has become less influential in Moore’s Law scaling. More specifically, for generations after the 130nm node (90nm, 65nm, 45nm, 32nm, and 22nm) performance enhancers (such as SiGe induced strain and high-k metal gate) have been added to continue to drive the transistor roadmap forward. This paper will address the past role that SiGe has played on enhancing CMOS transistor performance, and speculate on the role that SiGe will play in future technology generations.