A Compiled 100 MHz Programmable FIR Filter Chip for Data Acquisition

This paper presents a very high speed 8 tap FIR filter chip for data acquisition in particle detection experiments at CERN. A 17-bit input accuracy and an 80 MHz sample rate were both stringent requirements, which led to the adoption of a fast and regular modified bit-plane architecture. The chip has been implemented by a silicon compiler written for this application. The resulting area is a 110K transistors, 10 mm2 active area chip (in 0.7¿m CMOS technology) working at more than 100 MHz.