A Power Efficient, Oblivious, Path-Diverse, Minimal Routing for Mesh-based Networks-on-Chip
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[1] Juha Plosila,et al. Network on Chip Routing Algorithms , 2006 .
[2] Srinivas Devadas,et al. Path-based, Randomized, Oblivious, Minimal routing , 2009, 2009 2nd International Workshop on Network on Chip Architectures.
[3] Leslie G. Valiant,et al. Universal schemes for parallel communication , 1981, STOC '81.
[4] Giovanni De Micheli,et al. Design, synthesis, and test of networks on chips , 2005, IEEE Design & Test of Computers.
[5] Luca Benini,et al. Networks on Chips : A New SoC Paradigm , 2022 .
[6] Partha Pratim Pande,et al. Performance Evaluation of Adaptive Routing Algorithms for achieving Fault Tolerance in NoC Fabrics , 2007, 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP).
[7] S. Lennart Johnsson,et al. ROMM routing on mesh and torus networks , 1995, SPAA '95.
[8] W. Dally,et al. Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[9] G. Edward Suh,et al. Application-aware deadlock-free oblivious routing , 2009, ISCA '09.
[10] Lionel M. Ni,et al. Adaptive routing in mesh-connected networks , 1992, [1992] Proceedings of the 12th International Conference on Distributed Computing Systems.
[11] William J. Dally,et al. Principles and Practices of Interconnection Networks , 2004 .
[12] Sudhakar Yalamanchili,et al. Interconnection Networks: An Engineering Approach , 2002 .
[13] José Duato,et al. A Communication-Driven Routing Technique for Application-Specific NoCs , 2010, International Journal of Parallel Programming.
[14] Fernando Moraes,et al. Evaluation of Routing Algorithms on Mesh Based NoCs , 2004 .
[15] Z. Navabi,et al. Evaluation of pseudo adaptive XY routing using an object oriented model for NOC , 2005, 2005 International Conference on Microelectronics.
[16] Sameh A. Salem,et al. PPNOCS: Performance and Power Network on Chip Simulator based on SystemC , 2011 .
[17] Lionel M. Ni,et al. A survey of wormhole routing techniques in direct networks , 1993, Computer.
[18] Medhat Awadalla,et al. Network-on-Chip: Power Optimization Architecture Mapping based on Global Interconnection Links , 2011 .
[19] S. Martel,et al. System Design of an Integrated Measurement Electronic Subsystem for Bacteria Detection Using an Electrode Array and MC-1 Magnetotactic Bacteria , 2007, 2006 International Workshop on Computer Architecture for Machine Perception and Sensing.
[20] G. Edward Suh,et al. Static virtual channel allocation in oblivious routing , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.
[21] Akif Ali,et al. Near-optimal worst-case throughput routing for two-dimensional mesh networks , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).
[22] Russell Tessier,et al. ASOC: a scalable, single-chip communications architecture , 2000, Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622).
[23] S. Lennart Johnsson,et al. ROMM Routing: A Class of Efficient Minimal Routing Algorithms , 1994, PCRCW.