Semiconductor memory device and operating method thereof

The present invention relates to a semiconductor memory device. According to an embodiment of the present invention, a semiconductor memory device includes a memory cell, a page buffer including a first sensing latch unit and a second sensing latch unit connected to sensing nodes, respectively, through a first switching device and a second sensing latch unit, and a control logic configured to transmit a first sensing signal and a second sensing signal having different voltages to the first and second switching devices, respectively, upon performing a verification operation. The first and second switching devices are turned on or off in response to the first and second sensing signals, respectively.