Extensible and Configurable Processors for System-on-Chip Design
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F. Campi | J. Nurmi | S. Leibson | C. Panis
[1] Jari Nurmi,et al. FSEL - selective predicated execution for a configurable DSP core , 2004, IEEE Computer Society Annual Symposium on VLSI.
[2] Andrea Lodi,et al. A C-based algorithm development flow for a reconfigurable processor architecture , 2003, Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748).
[3] Andreas Krall,et al. XDSPCORE: a compiler-based configurable digital signal processor , 2004, IEEE Micro.
[4] Jari Nurmi,et al. COFFEE - a core for free , 2003, Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748).
[5] Roberto Guerrieri,et al. A VLIW processor with reconfigurable instruction set for embedded applications , 2003 .
[6] Jari Nurmi,et al. Reprogrammable Algorithm Accelerator IP Block , 2003, VLSI-SOC.
[7] Steve Leibson,et al. Configurable processors: a new era in chip design , 2005, Computer.
[8] C. Panis,et al. A scalable instruction buffer and align unit for xDSPcore , 2004, IEEE Journal of Solid-State Circuits.
[9] Jari Nurmi,et al. DSPxPlore: design space exploration methodology for an embedded DSP core , 2004, SAC '04.
[10] Jari Nurmi,et al. A FPGA Implementation of An Open-Source Floating-Point Computation System , 2005, 2005 International Symposium on System-on-Chip.