A New Low Power Single Bit Full Adder Design with 14 Transistors using Novel 3 Transistors XOR Gate

In present work a new XOR gate using three transistors has been proposed. Design shows adequate output logic levels with noise margin of 2V with 3.3V input signals. XNOR logic, obtained with addition of inverter shows improved noise margin of 3.2V. A new design for single bit full adder has been implemented using proposed XOR/XNOR gates and transmission gate multiplexer. Full adder designed with 14 transistors shows power dissipation of 655.6149μW and maximum output delay 0.11055ns. Proposed adder circuit shows adequate noise margin of 3.2 V for Sum (Sum output) and 2.2V for Cout (Carry output) with supply voltage of 3.3V. Circuit works well with reduced supply voltage and simulations have been carried out up to 1.8V supply voltage. Simulations are performed by using SPICE based on TSMC 0.35μm CMOS technology. Power consumption of proposed full adders has been compared with earlier reported circuits and proposed circuit’s shows better performance in terms of power consumptions and transistor count.

[1]  Wu-Shiung Feng,et al.  New efficient designs for XOR and XNOR functions on the transistor level , 1994, IEEE J. Solid State Circuits.

[2]  Wolfgang Fichtner,et al.  Low-power logic styles: CMOS versus pass-transistor logic , 1997, IEEE J. Solid State Circuits.

[3]  Mohamed A. Elgamel,et al.  Design methodologies for high-performance noise-tolerant XOR-XNOR circuits , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  Yuke Wang,et al.  Design and analysis of 10-transistor full adders using novel XOR-XNOR gates , 2000, WCC 2000 - ICSP 2000. 2000 5th International Conference on Signal Processing Proceedings. 16th World Computer Congress 2000.

[5]  Sudarshan Tiwari,et al.  New Design Methodologies for High Speed Low Power XOR-XNOR Circuits , 2009 .

[6]  Magdy A. Bayoumi,et al.  Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Edwin Hsing-Mean Sha,et al.  A novel multiplexer-based low-power full adder , 2004, IEEE Transactions on Circuits and Systems II: Express Briefs.

[8]  Kamran Eshraghian,et al.  Principles of CMOS VLSI Design: A Systems Perspective , 1985 .

[9]  S. Akashe,et al.  A novel high-performance CMOS 1 bit full-adder cell , 2013, 2013 7th International Conference on Intelligent Systems and Control (ISCO).

[10]  D. Radhakrishnan,et al.  Low-voltage low-power CMOS full adder , 2001 .

[11]  Lizy Kurian John,et al.  A novel low power energy recovery full adder cell , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

[12]  M.A. Bayoumi,et al.  A structured approach for designing low power adders , 1997, Conference Record of the Thirty-First Asilomar Conference on Signals, Systems and Computers (Cat. No.97CB36136).

[13]  Yingtao Jiang,et al.  Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates , 2002 .

[14]  Haomin Wu,et al.  A new design of the CMOS full adder , 1992 .

[15]  Yu-Cherng Hung,et al.  A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System , 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

[16]  Yuke Wang,et al.  New 4-transistor XOR and XNOR designs , 2000, Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434).

[17]  Wu-Shiung Feng,et al.  A new direct design for three-input XOR function on the transistor level , 1996 .

[18]  Tarek Darwish,et al.  Performance analysis of low-power 1-bit CMOS full adder cells , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[19]  Chip-Hong Chang,et al.  A novel hybrid pass logic with static CMOS output drive full-adder cell , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..