FPGA Design for Multiline Acquisition and Ethernet Interface in High-Frame-Rate Ultrasound Machines

ABSTRACT The study presents the design of a 32-channel field-programmable gate arrays (FPGA) for ultrasound instruments working at high frame rates of the order of 1000 fps. The FPGA does multiline acquisition and Ethernet framing of the received data stream from the analog-to-digital converters (ADCs). The study also presents implementation of innovative methods of moving window algorithm, critical window capture, and envelope detection in the FPGA, for data rate reduction to aid video processing in laptops. The FPGA has serial peripheral interfacing bus interface towards microcontroller. FPGA also has data interface towards ADCs and Gigabit Ethernet MAC device. The microcontroller has in-line management interface with Gigabit Ethernet MAC through the FPGA. The FPGA dataflow consists of received signal processing of captured ultrasound data from ADCs, temporary storage in FPGA, and forwarding to external Ethernet devices after Ethernet framing. All the functional blocks are integrated and synchronized with an external clock. Internal clock and control signal generation modules generate the requisite timing clocks. The FPGA design has been realized in prototype hardware. The prototype hardware has microcontroller-based control from a MATLAB-based graphical user interface for device configurations and image processing. The captured packets as well as the acquired image results are shown. The design is modular, flexible, have large-scale integration, cost-effective, and can be easily replicated.

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