semiconductor memory device

The present invention, type that, by applying a combination of the command signal in response to the control signal generating unit, a test signal for generating a test signal from the external mode is applied from an external setting signal of a test mode, the semiconductor memory device is separate resettable mode setting signal is individually set / specifying a reset signal if the response to the set / reset signal generating unit, a test signal for generating a first set / reset signal to store the mode set signal and a test logic unit for outputting a first set / receiving applying a reset signal and the test signal by combining the mode setting signal output from the semiconductor memory device set / reset master signal for outputting a set / reset master signal to common control in the test mode of the internal block generating unit, the test logic unit generating a plurality of control signals and responds to each of a plurality of control signals The test control signal is generated to open a set / reset signal is generated by the master each of a plurality of test control signals is characterized by comprising a. Thus it is possible to continuously test a semiconductor memory device without repeatedly executing tasks of multiple steps in the test mode for re-test if the the present invention to reduce the test execution time to promote the convenience of the test performed.