Device and reliability improvement of HfSiON+LaOx/metal gate stacks for 22nm node application

For the first time, we illustrate the importance of process sequence for LaOx capped HfSiON/metal gate on performance, variability, scaling, interface quality and reliability. La diffusion to the high-k/low-k interface controls V<sub>t</sub>, as well as strongly affects mobility, N<sub>it</sub> and BTI. La diffusion is limited to the Si surface by employing SiON interface layer (IL) mitigating the issues of La-induced mobility degradation and PBTI. Improved V<sub>t</sub> tunability, reliability and performance are achieved with optimized process sequence, high-k thickness control, LaOx deposition and SiON (not SiO<sub>2</sub>) IL. T<sub>inv</sub>=1.15 nm and V<sub>t,lin</sub>=0.31 V was obtained while achieving the following attributes: mobility~70%, N<sub>it</sub> <5times10<sup>10</sup> cm<sup>-2</sup>, DeltaV<sub>t</sub><30 m V within wafer, BTI DeltaV<sub>t</sub> <40 m V at 125degC. By optimizing these gate stack factors, we have developed and demonstrated structures for 22 nm node LOP application.

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