Device and reliability improvement of HfSiON+LaOx/metal gate stacks for 22nm node application
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G. Bersuker | R. Jammy | B.H. Lee | P. Majhi | J. Price | H.R. Harris | J. Huang | C.Y. Kang | C. Young | D. Heh | H.-H. Tseng | P.Y. Hung | D.C. Gilmer | P.D. Kirsch | P. Sivasubramani | M.A. Quevedo-Lopez | N. Goel | C.S. Park | C. Park | M. Hussain
[1] Y. Ohji,et al. Vth-tunable CMIS platform with high-k gate dielectrics and variability effect for 45nm node , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
[2] M. Ieong,et al. Band-Edge High-Performance High-k/Metal Gate n-MOSFETs Using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..
[3] R. Jammy,et al. Thermally Stable N-Metal Gate MOSFETs Using La-Incorporated HfSiO Dielectric , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..
[4] G. Bersuker,et al. nMOSFET Reliability Improvement attributed to the Interfacial Dipole formed by La Incorporation in HfO2 , 2007 .
[5] X. Chen,et al. A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process , 2008, 2008 Symposium on VLSI Technology.
[6] Massimo V. Fischetti,et al. Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks , 2003 .
[7] C. Adelmann,et al. Low VT metal-gate/high-k nMOSFETs — PBTI dependence and VT Tune-ability on La/Dy-capping layer locations and Laser annealing conditions , 2008, 2008 Symposium on VLSI Technology.
[8] Syed Muhammad Zain Zafar,et al. High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing , 2007, 2007 IEEE Symposium on VLSI Technology.
[9] S. De Gendt,et al. Low VT CMOS using doped Hf-based oxides, TaC-based Metals and Laser-only Anneal , 2007, 2007 IEEE International Electron Devices Meeting.
[10] D. Gilmer,et al. Microstructure modified HfO/sub 2/ using Zr addition with Ta/sub x/ C/sub y/ gate for improved device performance and reliability , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..