The Dynamic Evaluation Strategy for Evolvable Hardware

Evolvable hardware (EHW) has recently become a highly attractive topic for the Fault-tolerant System design because it offers a way of adapting hardware to different environments. However, it is time-consuming when circuits become complex. According to our research, the most time consuming period in genetic algorithm (GA) is the fitness evaluation. To reduce the time, a new method based on fitness evaluation expansion GA is proposed. The fitness evaluation is divided into two stages by a threshold. When the generation is lower than the threshold, a fitness estimate strategy is introduced to estimate the offspring's fitness. When really evolving the fitness, a self-adaptive random sampling model is applied to select the output node from the Cartesian Genetic Programming (CGP) array. During the evolution process, the random sampling probability can be adjusted dynamically with the concentration degree of individuals, which can short the evaluation time and accelerate the convergence. Experiments show that this method can obtain about 5 times speedup while getting an ideal circuit.

[1]  Yong-sheng Ding,et al.  Adaptive immune genetic algorithm for logic circuit design , 2009, GEC '09.

[2]  Ronald F. DeMara,et al.  Intrinsic evolvable hardware platform for digital circuit design and repair using genetic algorithms , 2012, Appl. Soft Comput..

[3]  Garrison W. Greenwood.  Attaining Fault Tolerance through Self-adaption: The Strengths and Weaknesses of Evolvable Hardware Approaches , 2008, WCCI.

[4]  Zhang Junbin,et al.  Genetic Algorithm Particle Swarm Optimization Based Hardware Evolution Strategy , 2014 .

[5]  Julian Francis Miller,et al.  Cartesian genetic programming , 2000, GECCO '10.

[6]  Zhu Xiao-hua.  Evolutionary Design of Gate-level Circuits Based on Fitness Evaluation Expansion Adaptive Genetic Algorithm , 2011 .

[7]  Zbigniew Michalewicz,et al.  Parameter Control in Evolutionary Algorithms , 2007, Parameter Setting in Evolutionary Algorithms.

[8]  Farouk Smith,et al.  Hardware evolution of a digital circuit using a custom VLSI architecture , 2013, SAICSIT '13.

[9]  Mehrdad Salami,et al.  The Fast Evaluation Strategy for Evolvable Hardware , 2005, Genetic Programming and Evolvable Machines.

[10]  Ronald F. DeMara,et al.  Designing digital circuits for FPGAs using parallel genetic algorithms (WIP) , 2012, SpringSim.

[11]  Fernando Santos Osório,et al.  Genetic Algorithms and Artificial Neural Networks to Combinational Circuit Generation on Reconfigurable Hardware , 2010, 2010 International Conference on Reconfigurable Computing and FPGAs.

[12]  V. Nicolau,et al.  A new Quantum Inspired Genetic Algorithm for Evolvable Hardware , 2010, 2010 3rd International Symposium on Electrical and Electronics Engineering (ISEEE).

[13]  Takahiro Watanabe,et al.  Efficient GA Approach Combined with Taguchi Method for Mixed Constrained Circuit Design , 2011, 2011 International Conference on Computational Science and Its Applications.

[14]  Xuejun Song,et al.  Optimization Algorithm of Evolutionary Design of Circuits Based on Genetic Algorithm , 2012, 2012 Fifth International Symposium on Computational Intelligence and Design.