26.5-30-GHz resistive mixer in 90-nm VLSI SOI CMOS technology with high linearity for WLAN

A resistive mixer with high linearity for wireless local area networks is presented in this paper. The fully integrated circuit is fabricated with a 90-nm very large scale integration silicon-on-insulator (SOI) CMOS technology and has a very compact size of 0.38 mm/spl times/0.32 mm. Design guidelines are given to optimize the circuit performance. Analytical calculations and simulations with an SOI large-signal Berkeley simulation model show good agreement with measurements. At an RF of 27 GHz, an IF of 2.5 GHz and zero dc power consumption, a conversion loss of 9.7 dB, a single-sideband noise figure of 11.4 dB, and a high third-order intercept point at the input of 20 dBm are measured at a local-oscillator (LO) power of 10 dBm. At lower LO power of 0-dBm LO power, the loss is 10.3 dB. To the knowledge of the author, the circuit has by far the highest operation frequency reported to date for a resistive CMOS mixer. Furthermore, it provides the highest linearity for a CMOS mixer operating at such high frequencies.