A 10Gb/s receiver with equalizer and on-chip ISI monitor in 0.11μm CMOS

This paper presents a IOGbis receiver that consists of an equalizer, an inter-symbol interference (ISI) monitor, and a clock and data recovety (CDR) unit. The Cherry-Hooper topology was employed to realize an adjustable highbandwidth equalizer with reduced area and power consumption, without using on-chip inductors. The IS1 monitor measures the post-cursor and pre-cursor IS1 in the equalizer output. The IS1 measurement is achieved using a switched-capacitor correlator. A test chip was fabricated in O.llpm CMOS. The areas and power consumptions are 47pm x S5pm and 13.2mW for the equalizer and 145pm x 80pm and lOmW for the IS1 monitor. Keyword: CMOS, equalizer, ISI, receiver, CDR

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