Optimization of Phase Noise in a 2:3 » 3:5GHz Voltage-controlled Oscillator Using the Impedance Locus
暂无分享,去创建一个
This work develops a 2:3 » 3:5GHz wideband voltage-controlled oscillator (VCO) using the impedance locus for both 802.11g and LTE-A applications. In this work, the operation bandwidth is expanded by using capacitor array. The phase noise performance is optimized by applying impedance locus design methodology. The analysis indicates that as the included angle approaches 90 - , the VCO exhibits a better phase noise performance. To conflrm the performance, a 2:3 » 3:5GHz wideband VCO is designed and implemented with TSMC 0.18"m CMOS technology. Measurements demonstrate that the wideband VCO design with phase noise optimization has a favorable phase noise and operation bandwidth performance. The phase noise is lower than i114dBc/Hz at the 1MHz ofiset frequencies over the 2:3 » 3:5GHz operation range.
[1] M. J. Howes,et al. A Reflection Coefficient Approach to the Design of One-Port Negative Impedance Oscillators , 1981 .
[2] T.H. Lee,et al. Oscillator phase noise: a tutorial , 1999, IEEE Journal of Solid-State Circuits.
[3] A. Hajimiri,et al. Design issues in CMOS differential LC oscillators , 1999, IEEE J. Solid State Circuits.
[4] Fred S. Lee,et al. A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator , 2010, IEEE Journal of Solid-State Circuits.