A Model for Soft Errors in the Subthreshold CMOS Inverter

—Soft errors are going to play an increasingly critical role in logic design, as power consumption drives CMOS scaling to ever lower supply voltages and device sizes. Both of these downscaling approaches contribute to significantly increased logic signal noise variance. This paper introduces a new methodology for predicting noise probability distributions for both equilibrium and non-equilibrium logic states of advanced CMOS inverters operated at low supply voltage. These distributions are essential to computing the probability of soft errors. The radiation-induced SER is not considered here.