Multi-level Logic Optimization By Implication Analysis

This paper proposes a new approach to multi-level logic optimization based on ATPG (Automatic Test Pattern Generation). Previous ATPG-based methods for logic minimization suffered from the limitation that they were quite restricted in the set of possible circuit transformations. We show that the ATPG-based method presented here allows (in principle) the transformation of a given combinational network C into an arbitrary, structurally different but functionally equivalent combinational network C'. Furthermore, powerful heuristics are presented in order to decide what network manipulations are promising for minimizing the circuit. By identifying indirect implications between signals in the circuit, transformations can be derived which are “good” candidates for the minimization of the circuit. In particular, it is shown that Recursive Learning can derive “good” Boolean divisors justifying the effort to attempt a Boolean division. For 9 out of 10 ISCAS-85 benchmark circuits our tool HANNIBAL obtains smaller circuits than the well-known synthesis system SIS.

[1]  Niraj K. Jha,et al.  Design and synthesis of self-checking VLSI circuits and systems , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[2]  Bill Lin,et al.  A generalized approach to the constrained cubical embedding problem , 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[3]  Yahiko Kambayashi,et al.  The Transduction Method-Design of Logic Networks Based on Permissible Functions , 1989, IEEE Trans. Computers.

[4]  Harold N. Gabow,et al.  Two Algorithms for Generating Weighted Spanning Trees in Order , 1977, SIAM J. Comput..

[5]  Stefano Manetti,et al.  SAPEC-a personal computer program for the symbolic analysis of electric circuits , 1988, 1988., IEEE International Symposium on Circuits and Systems.

[6]  Toshihide Ibaraki,et al.  Design of Optimal Switching Networks by Integer Programming , 1972, IEEE Transactions on Computers.

[7]  Albert R. Wang,et al.  Logic verification using binary decision diagrams in a logic synthesis environment , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[8]  Hideo Fujiwara,et al.  On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.

[9]  Roberto Guerrieri,et al.  Symbolic analysis of simplified transfer functions , 1993 .

[10]  M. Marek-Sadowska,et al.  Verifying equivalence of functions with unknown input correspondence , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[11]  Flávio Rech Wagner,et al.  Design Version Management in the STAR Framework , 1992, Electronic Design Automation Frameworks.

[12]  Janusz Rajski,et al.  The testability-preserving concurrent decomposition and factorization of Boolean expressions , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Melvin A. Breuer,et al.  Reconfigurable scan chains: A novel approach to reduce test application time , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[14]  Elizabeth M. Rudnick,et al.  Non-Scan Design-for-Testability Techniques for Sequential Circuits , 1993, 30th ACM/IEEE Design Automation Conference.

[15]  A. Rodríguez-Vázquez,et al.  Formula approximation for flat and hierarchical symbolic analysis , 1993 .

[16]  Harry F. Jordan,et al.  Time multiplexed optical computers , 1991, Proceedings of the 1991 ACM/IEEE Conference on Supercomputing (Supercomputing '91).

[17]  Brian W. Kernighan,et al.  An efficient heuristic procedure for partitioning graphs , 1970, Bell Syst. Tech. J..

[18]  Robert E. Tarjan,et al.  Data structures and network algorithms , 1983, CBMS-NSF regional conference series in applied mathematics.

[19]  Resve Saleh,et al.  Simulation and analysis of transient faults in digital circuits , 1992 .

[20]  G. C. Messenger,et al.  Collection of Charge on Junction Nodes from Ion Tracks , 1982, IEEE Transactions on Nuclear Science.

[21]  Sungju Park,et al.  A Graph Theoretic Approach to Partial Scan Design by K-Cycle Elimination , 1992, Proceedings International Test Conference 1992.

[22]  A.L. Sangiovanni-Vincentelli,et al.  A survey of optimization techniques for integrated-circuit design , 1981, Proceedings of the IEEE.

[23]  Robert K. Brayton,et al.  Timing analysis and delay-fault test generation using path-recursive functions , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[24]  Robert K. Brayton,et al.  Integrating functional and temporal domains in logic design , 1991 .

[25]  G. Persky.  PRO - an automatic string placement program for polycell layout , 1976, DAC '76.

[26]  Janak H. Patel,et al.  HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..

[27]  P. Van der Wolf.  Architecture of an open and efficient CAD framework , 1993 .

[28]  Leon L. Wu,et al.  Physical and electrical design features of the IBM Enterprise System/9000 circuit module , 1992, IBM J. Res. Dev..

[29]  Jason Cong,et al.  Provably good performance-driven global routing , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[30]  Jason Cong,et al.  An Efficient Multilayer MCM Router Based on Four-Via Routing , 1993, 30th ACM/IEEE Design Automation Conference.

[31]  Massoud Pedram,et al.  Layout driven technology mapping , 1991, 28th ACM/IEEE Design Automation Conference.

[32]  J. Paul Roth,et al.  Diagnosis of automata failures: a calculus and a method , 1966 .

[33]  Claude E. Shannon,et al.  A symbolic analysis of relay and switching circuits , 1938, Transactions of the American Institute of Electrical Engineers.

[34]  Ping Yang,et al.  Statistical modeling for efficient parametric yield estimation of MOS VLSI circuits , 1983, 1983 International Electron Devices Meeting.

[35]  R J Feuerstein,et al.  Implementation of a fiber-optic delay-line memory. , 1992, Applied optics.

[36]  C. L. Liu,et al.  Minimum crosstalk channel routing , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[37]  Reinaldo A. Bergamaschi,et al.  Timing analysis in high-level synthesis , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[38]  Ulrich Lauther,et al.  Congestion-driven placement using a new multi-partitioning heuristic , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[39]  P. M. Lin,et al.  A new network approach to symbolic simulation of large-scale networks , 1989, IEEE International Symposium on Circuits and Systems,.

[40]  Ernest S. Kuh,et al.  A spacing algorithm for performance enhancement and cross-talk reduction , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[41]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[42]  James A. McHugh,et al.  Algorithmic Graph Theory , 1986 .

[43]  Ulrich Lauther,et al.  A Min-Cut Placement Algorithm for General Cell Assemblies Based on a Graph Representation , 1979, 16th Design Automation Conference.

[44]  Ravishankar K. Iyer,et al.  Analog-digital simulation of transient-induced logic errors and upset susceptibility of an advanced control system , 1990 .

[45]  Massoud Pedram,et al.  Alleviating routing congestion by combining logic resynthesis and linear placement , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[46]  Silvano Gai,et al.  Fast differential fault simulation by dynamic fault ordering , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[47]  David P. LaPotin.  EARLY ASSESSMENT OF DESIGN, PACKAGING AND TECHNOLOGY TRADEOFFS , 1991 .

[48]  Thomas W. Parsons,et al.  Digital signal processing: theory, applications, and hardware , 1991 .

[49]  R. K. Brayton,et al.  Graph algorithms for clock schedule optimization , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[50]  Daniel Tabak,et al.  Microcontrollers: architecture, implementation, and programming , 1992 .

[51]  Wolfgang Kunz.  HANNIBAL: an efficient tool for logic verification based on recursive learning , 1993, ICCAD.

[52]  Gajski,et al.  Guest Editors' Introduction: New VLSI Tools , 1983, Computer.

[53]  A. Sangiovanni-Vincentelli,et al.  Constraint-based channel routing for analog and mixed analog/digital circuits , 1990, ICCAD 1990.

[54]  Gerard N. Stenbakken,et al.  LINEAR ERROR MODELING OF ANALOG AND MIXED-SIGNAL DEVICES , 1991, 1991, Proceedings. International Test Conference.

[55]  Maria J. Avedillo,et al.  SMAS: a program for the concurrent state reduction and state assignment of finite state machines , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[56]  V. Chaiyakul,et al.  Accurate layout area and delay modeling for system level design , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[57]  David Lawrence Johannsen.  Silicon compilation , 1989 .

[58]  J. H. ter Bekke.  Semantic data modeling , 1992 .

[59]  Janak H. Patel,et al.  PROOFS: a super fast fault simulator for sequential circuits , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[60]  Andrew B. Kahng,et al.  A new class of iterative Steiner tree heuristics with good performance , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[61]  Kurt Keutzer,et al.  Estimation of average switching activity in combinational and sequential circuits , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[62]  George E. P. Box,et al.  Empirical Model‐Building and Response Surfaces , 1988 .

[63]  S.M. Reddy,et al.  On determining scan flip-flops in partial-scan designs , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[64]  Giovanni De Micheli,et al.  Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[65]  Donald E. Carter,et al.  Ce Concurrent Engineering: The Product Development Environment for the 1990s , 1992 .

[66]  Silvano Gai,et al.  The performance of the concurrent fault simulation algorithms in MOZART , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[67]  V P Heuring,et al.  Delay synchronization in time-of-flight optical systems. , 1992, Applied optics.

[68]  Ren-Song Tsay,et al.  Early wirability checking and 2D congestion-driven circuit placement , 1992, [1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit.

[69]  R. K. Brayton,et al.  Valid clocking in wavepipelined circuits , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[70]  J. Starzyk,et al.  Flowgraph analysis of large electronic networks , 1986 .

[71]  Robert K. Brayton,et al.  Sequential circuit design using synthesis and optimization , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[72]  Ernest S. Kuh,et al.  Quadratic Boolean Programming for Performance-Driven System Partitioning , 1993, 30th ACM/IEEE Design Automation Conference.

[73]  S.M. Kang,et al.  Fast And Accurate Timing Simulation With Regionwise Quadratic Models Of Mos I-V Characteristics , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[74]  Michael H. Schulz,et al.  SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[75]  Bernd Becker,et al.  Hierarchical Design Based on a Calculus of Nets , 1987, 24th ACM/IEEE Design Automation Conference.

[76]  M.G.R. Degrauwe,et al.  A symbolic analysis tool for analog circuit design automation , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[77]  Michael Weber,et al.  Detection of symmetry of Boolean functions represented by ROBDDs , 1993, ICCAD '93.

[78]  Hiroyuki Ochi,et al.  Breadth-first manipulation of very large binary-decision diagrams , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[79]  LaNae J. Avra,et al.  ALLOCATION AND ASSIGNMENT IN HIGH-LEVEL SYNTHESIS FOR SELF-TESTABLE DATA PATHS , 1991, 1991, Proceedings. International Test Conference.

[80]  Trevor N. Mudge,et al.  CheckT/sub c/ and minT/sub c/: timing verification and optimal clocking of synchronous digital circuits , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[81]  Wai-Kai Chen,et al.  Graph theory , 1972 .

[82]  Minh N. Do,et al.  Youn-Long Steve Lin , 1992 .

[83]  James E. Smith,et al.  Strongly Fault Secure Logic Networks , 1978, IEEE Transactions on Computers.

[84]  Masahiro Fujita,et al.  On variable ordering of binary decision diagrams for the application of multi-level logic synthesis , 1991, Proceedings of the European Conference on Design Automation..

[85]  G. Dueck.  New optimization heuristics , 1993 .

[86]  W.-T. Cheng,et al.  The BACK algorithm for sequential test generation , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[87]  Sujit Dey,et al.  Clock Period Optimization During Resource Sharing and Assignment , 1994, 31st Design Automation Conference.

[88]  J. Altmeyer,et al.  On Modeling Top-down VLSI Design , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[89]  R. I. Bahar,et al.  Algebraic decision diagrams and their applications , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[90]  R. Dandapani,et al.  Scan Design Using Standard Flip-Flops , 1987, IEEE Design & Test of Computers.

[91]  Daniel Brand.  Redundancy and Don't Cares in Logic Synthesis , 1983, IEEE Transactions on Computers.

[92]  Rob A. Rutenbar,et al.  ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits , 1994, 31st Design Automation Conference.

[93]  D.J. Blumenthal,et al.  First demonstration of multihop all-optical packet switching , 1994, IEEE Photonics Technology Letters.

[94]  Ernest S. Kuh,et al.  Glitter: A Gridless Variable-Width Channel Router , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[95]  Sharad Malik,et al.  Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications , 1994, 31st Design Automation Conference.

[96]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[97]  Kwang-Ting Cheng,et al.  Sequential logic optimization by redundancy addition and removal , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[98]  Bonnie Berger,et al.  Approximation alogorithms for the maximum acyclic subgraph problem , 1990, SODA '90.

[99]  R. M. Mattheyses,et al.  A Linear-Time Heuristic for Improving Network Partitions , 1982, 19th Design Automation Conference.

[100]  Kurt Keutzer.  DAGON: Technology Binding and Local Optimization by DAG Matching , 1987, DAC.

[101]  Bill Lin,et al.  Minimization of symbolic relations , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[102]  Reinaldo A. Bergamaschi,et al.  The effects of false paths in high-level synthesis , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[103]  Srinivas Devadas,et al.  Optimum and heuristic algorithms for an approach to finite state machine decomposition , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[104]  Wentai Liu,et al.  Timing constraints for wave-pipelined systems , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[105]  Robert K. Brayton,et al.  Extracting local don't cares for network optimization , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[106]  Sung-Mo Kang,et al.  Analytic transient solution of general MOS circuit primitives , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[107]  Georges Gielen,et al.  ISAAC: a symbolic simulator for analog integrated circuits , 1989, IEEE J. Solid State Circuits.

[108]  David Hung-Chang Du,et al.  Path sensitization in critical path problem , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[109]  R J Feuerstein,et al.  Implementation of a general-purpose stored-program digital optical computer. , 1994, Applied optics.

[110]  D. G. Saab,et al.  Behavioral synthesis for testability , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[111]  Emil F. Girczyc,et al.  Increasing Design Quality and Engineering Productivity through Design Reuse , 1993, 30th ACM/IEEE Design Automation Conference.

[112]  Miodrag Potkonjak,et al.  Exploiting hardware sharing in high-level synthesis for partial scan optimization , 1993, ICCAD '93.

[113]  S.K. Gupta,et al.  Can concurrent checkers help BIST? , 1992, Proceedings International Test Conference 1992.

[114]  Janak H. Patel,et al.  PROOFS: a fast, memory-efficient sequential circuit fault simulator , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[115]  Dhiraj K. Pradhan,et al.  Recursive Learning: An attractive alternative to the decision tree for test generation in digital ci , 1992, Proceedings International Test Conference 1992.

[116]  Christos A. Papachristou,et al.  A built-in self-testing approach for minimizing hardware overhead , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[117]  Kwang-Ting Cheng,et al.  Sequential logic optimization by redundancy addition and removal , 1993, ICCAD.

[118]  Robert K. Brayton,et al.  Logic Minimization Algorithms for VLSI Synthesis , 1984, The Kluwer International Series in Engineering and Computer Science.

[119]  Peter Freeman,et al.  Classifying Software for Reusability , 1987, IEEE Software.

[120]  Dong Sam Ha,et al.  AN EFFICIENT, FORWARD FAULT SIMULATION ALGORITHM BASED ON THE PARALLEL PATTERN SINGLE FAULT PROPAGAT , 1991, 1991, Proceedings. International Test Conference.

[121]  Maria Brielmann,et al.  Representing the hardware design process by a common data schema , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

[122]  Srinivas Devadas,et al.  Sequential Logic Testing and Verification , 1991 .

[123]  Günter Hotz.  Einführung in die Informatik , 1990, Leitfäden und Monographien der Informatik.

[124]  Robert B. Hitchcock,et al.  Timing verification and the timing analysis program , 1988, DAC 1982.

[125]  Ramesh Harjani,et al.  Feasibility region modeling of analog circuits for hierarchical circuit design , 1994, Proceedings of 1994 37th Midwest Symposium on Circuits and Systems.

[126]  Régis Leveugle.  Optimized State Assignment of Single Fault Tolerant FSMs Based on SEC Codes , 1993, 30th ACM/IEEE Design Automation Conference.

[127]  Georges Gielen,et al.  Symbolic analysis for automated design of analog integrated circuits , 1991, The Kluwer international series in engineering and computer science.

[128]  Miodrag Potkonjak,et al.  Transforming behavioral specifications to facilitate synthesis of testable designs , 1994, Proceedings., International Test Conference.

[129]  Sung-Mo Kang,et al.  Crosstalk-minimum layer assignment , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[130]  S.-M. Chang,et al.  Matrix reduction and numerical approximation during computation techniques for symbolic analog circuit analysis , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[131]  Don MacMillen,et al.  ISIS: a system for performance driven resource sharing , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[132]  Thomas G. Szymanski,et al.  Computing optimal clock schedules , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[133]  Alberto Sangiovanni-Vincentelli,et al.  TimberWolf3.2: A New Standard Cell Placement and Global Routing Package , 1986, DAC 1986.

[134]  Alexandros Biliris,et al.  Database Support for Evolving Design Objects , 1989, 26th ACM/IEEE Design Automation Conference.

[135]  Nikolaus Gouders,et al.  PARIS: a parallel pattern fault simulator for synchronous sequential circuits , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[136]  Dong Sam Ha,et al.  HOPE: an efficient parallel fault simulator for synchronous sequential circuits , 1992, DAC '92.

[137]  G. Sigl,et al.  GORDIAN: a new global optimization/rectangle dissection method for cell placement , 1988, ICCAD 1988.

[138]  C.-J. Richard Shi,et al.  Efficient constrained encoding for VLSI sequential logic synthesis , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

[139]  Janak H. Patel,et al.  An optimization based approach to the partial scan design problem , 1990, Proceedings. International Test Conference 1990.

[140]  Carl Sechen,et al.  Fully symbolic analysis of large analog integrated circuits , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[141]  H. Fujiwara,et al.  ON THE ACCELERATION OF TEST GENERATION ALGORlTHMS , 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing, 1995, ' Highlights from Twenty-Five Years'..

[142]  Georges Gielen,et al.  Symbolic analysis methods and applications for analog circuits: a tutorial overview , 1994, Proc. IEEE.

[143]  Pinaki Mazumder,et al.  VLSI cell placement techniques , 1991, CSUR.

[144]  Qinhai Zhang,et al.  Advanced ordering and manipulation techniques for binary decision diagrams , 1992, [1992] Proceedings The European Conference on Design Automation.

[145]  T.M. Souders,et al.  Cutting the high cost of testing , 1991, IEEE Spectrum.

[146]  Maciej J. Ciesielski,et al.  A unified approach to input-output encoding for FSM state assignment , 1991, 28th ACM/IEEE Design Automation Conference.

[147]  Franc Brglez,et al.  Introduction of permissible bridges with application to logic optimization after technology mapping , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[148]  F.J. Kurdahi,et al.  Combined topological and functionality based delay estimation using at layout-driven approach for high level applications , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

[149]  Yoshiyasu Takefuji,et al.  Databases and cell-selection algorithms for VLSI cell libraries , 1990, Computer.

[150]  Jack Kiefer,et al.  Collected Papers III: Design of Experiments , 1984 .

[151]  Jon R. Sauer,et al.  Design and implementation of a prototype optical deflection network , 1994, SIGCOMM 1994.

[152]  Paolo Prinetto,et al.  A diagnostic test pattern generation algorithm , 1990, Proceedings. International Test Conference 1990.

[153]  John K. Ousterhout,et al.  Tcl: An Embeddable Command Language , 1989, USENIX Winter.

[154]  Prithviraj Banerjee,et al.  RSYN: a system for automated synthesis of reliable multilevel circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[155]  A. Lempel,et al.  Minimum Feedback Arc and Vertex Sets of a Directed Graph , 1966 .

[156]  Régis Leveugle,et al.  Taking advantage of high level functional information to refine timing analysis and timing information , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[157]  E. Felt,et al.  Analog testability analysis and fault diagnosis using behavioral modeling , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[158]  Hiroo Masuda,et al.  A New Design-Centering Methodology for VLSI Device Development , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[159]  Miodrag Potkonjak,et al.  Fast prototyping of datapath-intensive architectures , 1991, IEEE Design & Test of Computers.

[160]  Hugo De Man,et al.  Static Timing Analysis of Dynamically Sensitizable Paths , 1989, 26th ACM/IEEE Design Automation Conference.

[161]  Rob A. Rutenbar,et al.  OASYS: a framework for analog circuit synthesis , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[162]  Maciej J. Ciesielski,et al.  Clock period minimization with wave pipelining , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[163]  Gerhard Zimmermann,et al.  PLAYOUT - A Hierarchical Design System , 1989, IFIP Congress.

[164]  Janak H. Patel,et al.  A fault oriented partial scan design approach , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[165]  Hiroshi Sawada,et al.  Minimization of binary decision diagrams based on exchanges of variables , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[166]  Shin-ichi Minato,et al.  Zero-Suppressed BDDs for Set Manipulation in Combinatorial Problems , 1993, 30th ACM/IEEE Design Automation Conference.

[167]  Yen-Chuen A. Wei,et al.  Circuit partitioning and its applications to vlsi designs , 1990 .

[168]  Resve A. Saleh,et al.  Exact evaluation of diagnostic test resolution , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[169]  P. Lin.  Symbolic network analysis , 1991 .

[170]  Jonathan Allen,et al.  Performance-directed synthesis of VLSI systems , 1990, Proc. IEEE.

[171]  Nikil D. Dutt,et al.  Rapid estimation for parameterized components in high-level synthesis , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[172]  Alberto L. Sangiovanni-Vincentelli,et al.  A behavioral representation for Nyquist rate A/D converters , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[173]  Chen-Shang Lin,et al.  Parallel sequence fault simulation for synchronous sequential circuits , 1992, [1992] Proceedings The European Conference on Design Automation.

[174]  Dong Sam Ha,et al.  New methods of improving parallel fault simulation in synchronous sequential circuits , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[175]  Ravishankar K. Iyer,et al.  A Measurement-Based Model for Workload Dependence of CPU Errors , 1986, IEEE Transactions on Computers.

[176]  Randy H. Katz,et al.  A Version Server for Computer-Aided Design Data , 1986, DAC 1986.

[177]  Tae Sun Kim,et al.  An Efficient Method for Optimal BDD Ordering Computation , 1993 .

[178]  A. Tversky.  Features of Similarity , 1977 .

[179]  Masahiro Fujita,et al.  Application of Boolean unification to combinational logic synthesis , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[180]  Janusz Rajski,et al.  A method to calculate necessary assignments in algorithmic test pattern generation , 1990, Proceedings. International Test Conference 1990.

[181]  Gary D. Hachtel,et al.  Performance enhancements in BOLD using 'implications' , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[182]  Malgorzata Marek-Sadowska,et al.  Detecting Symmetric Variables in Boolean Functions using Generalized Reel-Muller Forms , 1994, ISCAS.

[183]  Sharad Malik,et al.  Delay computation in combinational logic circuits: theory and algorithms , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[184]  K.-T. Cheng,et al.  A Partial Scan Method for Sequential Circuits with Feedback , 1990, IEEE Trans. Computers.

[185]  C.Y.R. Chen,et al.  Datapath cell design strategy for channelless routing , 1994, Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit.

[186]  Edward J. McCluskey,et al.  Design of Totally Self-Checking Comparators with an Arbitrary Number of Inputs , 1984, IEEE Transactions on Computers.

[187]  Carl Sechen,et al.  Low-frequency symbolic analysis of large analog integrated circuits , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[188]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[189]  R. Burkard,et al.  A heuristic for quadratic Boolean programs with applications to quadratic assignment problems , 1983 .

[190]  Ernst Siepmann,et al.  An Object-Oriented Datamodel for the VLSI Design System PLAYOUT , 1989, 26th ACM/IEEE Design Automation Conference.

[191]  Alberto L. Sangiovanni-Vincentelli,et al.  Minimizing production test time to detect faults in analog circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[192]  Cheng-Shiang Chiang.  A perturbation approach to the symbolic analysis of analog circuits , 1992 .

[193]  Seiyang Yang,et al.  Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[194]  Robert K. Brayton,et al.  Incremental synthesis for engineering changes , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[195]  Partha Chakrabarti,et al.  A New Approach For Factorizing FSM's , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[196]  Randy H. Katz,et al.  Toward a unified framework for version modeling in engineering databases , 1990, CSUR.

[197]  A.L. Sangiovanni-Vincentelli,et al.  Techniques For Crosstalk Avoidance In The Physical Design Of High-performance Digital Systems , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[198]  Edward J. McCluskey,et al.  Synthesizing for scan dependence in built-in self-testable designs , 1993, Proceedings of IEEE International Test Conference - (ITC).

[199]  Randal E. Bryant,et al.  Efficient implementation of a BDD package , 1991, DAC '90.

[200]  A. Richard Newton,et al.  Implicit manipulation of equivalence classes using binary decision diagrams , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[201]  W. Fichtner,et al.  Lazy-expansion symbolic expression approximation in SYNAP , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[202]  Fadi J. Kurdahi,et al.  Combined topological and functionality based delay estimation using a layout-driven approach for high level applications , 1994, EURO-DAC '92.

[203]  Yung-Te Lai,et al.  Edge-valued binary decision diagrams for multi-level hierarchical verification , 1992, DAC '92.

[204]  Robert K. Brayton,et al.  Optimal State Assignment for Finite State Machines , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[205]  J. A. Kuhn,et al.  Digital-compatible high-performance operational amplifier with rail-to-rail input and output ranges , 1994 .

[206]  Robert K. Brayton,et al.  MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[207]  S. B. Crary.  Optimal design of experiments for sensor calibration , 1991, TRANSDUCERS '91: 1991 International Conference on Solid-State Sensors and Actuators. Digest of Technical Papers.

[208]  Elizabeth M. Rudnick,et al.  Diagnostic Fault Simulation of Sequential Circuits , 1992, Proceedings International Test Conference 1992.

[209]  Richard Edwin Stearns,et al.  Some Dangers in State Reduction of Sequential Machines , 1962, Inf. Control..

[210]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[211]  Alan J. Miller,et al.  A review of some exchange algorithms for constructing discrete D-optimal designs , 1992 .

[212]  Robert Hooke,et al.  `` Direct Search'' Solution of Numerical and Statistical Problems , 1961, JACM.

[213]  Ronald L. Rivest,et al.  Introduction to Algorithms , 1990 .

[214]  Janak H. Patel,et al.  A comparative study of design for testability methods using high-level and gate-level descriptions , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[215]  S. Davidson,et al.  Sequential Circuit Test Generator (STG) benchmark results , 1989, IEEE International Symposium on Circuits and Systems,.

[216]  Bryan D. Ackland,et al.  Physical Design Automation of Vlsi Systems , 1988 .

[217]  M. Richter.  Classification and Learning of Similarity Measures , 1993 .

[218]  Sung-Mo Kang,et al.  Detailed layer assignment for MCM routing , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[219]  Wayne Wei-Ming Dai,et al.  Rubber band routing and dynamic data representation , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[220]  Louise Trevillyan,et al.  Global flow optimization in automatic logic design , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[221]  Carl Sechen,et al.  Efficient and effective placement for very large circuits , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[222]  Sujit Dey,et al.  Transformations and resynthesis for testability of RT-level control-data path specifications , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[223]  Victor R. Basili,et al.  Support for comprehensive reuse , 1991, Softw. Eng. J..

[224]  A. Sangiovanni-Vincentelli,et al.  A synthesis and optimization procedure for fully and easily testable sequential machines , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[225]  H. H. Chen,et al.  Wiring And Crosstalk Avoidance In Multi-chip Module Design , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[226]  Sujit Dey,et al.  Provably Correct High-level Timing Analysis Without Path Sensitization , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[227]  R. Rudell.  Dynamic variable ordering for ordered binary decision diagrams , 1993, ICCAD 1993.

[228]  Daniel Brand.  Verification of large synthesized designs , 1993, ICCAD.

[229]  Georges Gielen,et al.  A cancellation-free algorithm for the symbolic simulation of large analog circuits , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[230]  P. Wambacq,et al.  Efficient symbolic computation of approximated small-signal characteristics , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[231]  A. Rodríguez-Vázquez,et al.  Interactive AC modeling and characterization of analog circuits via symbolic analysis , 1991 .

[232]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[233]  E. M. L. Beale,et al.  Nonlinear and Dynamic Programming , 1965 .

[234]  J. S. Hunter,et al.  Statistics for experimenters : an introduction to design, data analysis, and model building , 1979 .

[235]  Melvin A. Breuer,et al.  BALLAST: a methodology for partial scan design , 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[236]  Masahiro Fujita,et al.  Rectification method for lookup-table type FPGA's , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[237]  K. S. Kim,et al.  Partial scan by use of empirical testability , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[238]  Anja Feldmann,et al.  HERO: Hierarchical EMC-constrained routing , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[239]  Wu-Tung Cheng,et al.  Gentest: an automatic test-generation system for sequential circuits , 1989, Computer.

[240]  Qicheng Yu,et al.  Generation of color-constrained spanning trees with application in symbolic circuit analysis , 1994, Proceedings of 4th Great Lakes Symposium on VLSI.

[241]  Maciej Ciesielski,et al.  Layer assignment for printed circuit boards and integrated circuits , 1992, Proc. IEEE.

[242]  Won Kim,et al.  Modeling concepts for VLSI CAD objects , 1985, TODS.

[243]  M. Hassoun,et al.  Symbolic analysis of large-scale networks using a hierarchical signal flowgraph approach , 1993 .

[244]  Srinivas Devadas,et al.  Decomposition and factorization of sequential finite state machines , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[245]  E.S. Kuh,et al.  PROUD: a sea-of-gates placement algorithm , 1988, IEEE Design & Test of Computers.

[246]  Robert K. Brayton,et al.  Dynamic variable reordering for BDD minimization , 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.

[247]  Elizabeth M. Rudnick,et al.  A fast and accurate gate-level transient fault simulation environment , 1993, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing.

[248]  Dennis L. Young,et al.  Application of statistical design and response surface methods to computer-aided VLSI device design , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[249]  J. Soukup.  Circuit layout , 1981, Proceedings of the IEEE.

[250]  Nur A. Touba,et al.  Logic Synthesis for Concurrent Error Detection , 1993 .

[251]  Sharad Malik,et al.  Functional timing analysis using ATPG , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[252]  R. H. Hardin,et al.  A new approach to the construction of optimal designs , 1993 .

[253]  Christos H. Papadimitriou,et al.  The 1-Steiner Tree Problem , 1987, J. Algorithms.

[254]  Janet L. Kolodner,et al.  Case-Based Reasoning , 1989, IJCAI 1989.

[255]  Janusz Rajski,et al.  Testability preserving transformations in multi-level logic synthesis , 1990, Proceedings. International Test Conference 1990.

[256]  Narendra V. Shenoy,et al.  Verifying clock schedules , 1992, ICCAD 1992.

[257]  Chak-Kuen Wong,et al.  Layer assignment for multichip modules , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[258]  Christos A. Papachristou,et al.  An improved method for RTL synthesis with testability tradeoffs , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).