Embedded deterministic test for low-cost manufacturing
暂无分享,去创建一个
[1] Nur A. Touba,et al. Test vector encoding using partial LFSR reseeding , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[2] Huaguo Liang,et al. Two-dimensional test data compression for scan-based deterministic BIST , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[3] Janusz Rajski,et al. High speed ring generators and compactors of test data [logic IC test] , 2003, Proceedings. 21st VLSI Test Symposium, 2003..
[4] Brion L. Keller,et al. OPMISR: the foundation for compressed ATPG vectors , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[5] Alex Orailoglu,et al. Test volume and application time reduction through scan chain concealment , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[6] Nur A. Touba,et al. Scan vector compression/decompression using statistical coding , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).
[7] Nilanjan Mukherjee,et al. Embedded deterministic test , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[8] B. Koneman,et al. LFSR-Coded Test Patterns for Scan Designs , 1993 .
[9] Janak H. Patel,et al. Reducing test application time for built-in-self-test test pattern generators , 2000, Proceedings 18th IEEE VLSI Test Symposium.
[10] Bernard Courtois,et al. Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers , 1995, IEEE Trans. Computers.
[11] Brion L. Keller,et al. A SmartBIST variant with guaranteed encoding , 2001, Proceedings 10th Asian Test Symposium.
[12] Hans-Joachim Wunderlich,et al. Tailoring ATPG for embedded testing , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).