Exploiting the HTX-Board as a Coprocessor for Exact Arithmetics

Certain numerical computations benefit from dedicated computation units, e.g. providing increased computation accuracy. Exploiting current interconnection technologies and advances in reconfigurable logic, restrictions and drawbacks of past approaches towards application-specific units can be overcome. This paper presents our implementation of an FPGA-based hardware unit for exact arithmetics. The unit is tightly integrated into the host system using state-of-the-art HyperTransport technology. An according runtime system provides OS-level support including dynamic function resolution. The approach demonstrates suitability and applicability of the chosen technologies, setting the pace towards broadly acceptable use of reconfigurable coprocessor technology for application-specific computing.

[1]  Tarek A. El-Ghazawi,et al.  Bringing High-Performance Reconfigurable Computing to Exact Computations , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[2]  Christoforos E. Kozyrakis,et al.  A case for intelligent RAM , 1997, IEEE Micro.

[3]  Eric M. Schwarz,et al.  P6 Binary Floating-Point Unit , 2007, 18th IEEE Symposium on Computer Arithmetic (ARITH '07).

[4]  Michael Kroener,et al.  Binary Floating-Point Unit , 2007 .

[5]  Ulrich W. Kulisch,et al.  Advanced Arithmetic for the Digital Computer, Design of Arithmetic Units , 2002, RealComp.

[6]  Michael J. Liebelt,et al.  Multiple-precision fixed-point vector multiply-accumulator using shared segmentation , 2003, Proceedings 2003 16th IEEE Symposium on Computer Arithmetic.

[7]  Rob A. Rutenbar,et al.  Floating-point error analysis based on affine arithmetic , 2003, 2003 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03)..

[8]  Milind Girkar,et al.  EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system , 2007, PLDI '07.

[9]  Eric M. Schwarz,et al.  High performance floating-point unit with 116 bit wide divider , 2003, Proceedings 2003 16th IEEE Symposium on Computer Arithmetic.

[10]  J. Rokne.  Interval arithmetic and interval analysis: an introduction , 2001 .

[11]  Stamatis Vassiliadis,et al.  The MOLEN polymorphic processor , 2004, IEEE Transactions on Computers.

[12]  Ramon E. Moore.  Interval arithmetic and automatic error analysis in digital computing , 1963 .

[13]  Wolfgang Karl,et al.  A Light-Weight Approach to Dynamical Runtime Linking Supporting Heterogenous, Parallel, and Reconfigurable Architectures , 2009, ARCS.

[14]  Vincent Lefèvre,et al.  MPFR: A multiple-precision binary floating-point library with correct rounding , 2007, TOMS.

[15]  Thomas L. Sterling,et al.  Analysis and Modeling of Advanced PIM Architecture Design Tradeoffs , 2004, Proceedings of the ACM/IEEE SC2004 Conference.

[16]  David Slogsnat,et al.  The HTX-Board : A Rapid Prototyping Station , 2005 .

[17]  Shan Shan Huang,et al.  Liquid Metal: Object-Oriented Programming Across the Hardware/Software Boundary , 2008, ECOOP.

[18]  Christoph Baumhof,et al.  A CMOS Floating-Point Processing Chip for Verified Exact Vector Arithmetic , 1994, ESSCIRC '94: Twientieth European Solid-State Circuits Conference.

[19]  Ulrich Brüning,et al.  An open-source HyperTransport core , 2008, TRETS.

[20]  Jonathan W. Berry,et al.  Graph Analysis with High-Performance Computing , 2008, Computing in Science & Engineering.

[21]  Ulrich W. Kulisch,et al.  The XSC tools for extended scientific computing , 1996, Quality of Numerical Software.

[22]  Peter-Michael Seidel.  High-radix implementation of IEEE floating-point addition , 2005, 17th IEEE Symposium on Computer Arithmetic (ARITH'05).