Power Optimization and Prediction Techniques for FPGAs

Field-programmable gate arrays (FPGAs) are a popular choice for digital circuit implementation because of their growing density and speed, short design cycle, and steadily decreasing cost. Power consumption, specifically leakage power, has become a major concern for the semiconductor industry and its customers. FPGAs are less power-efficient than custom ASICs, due to the overhead required to provide programmability. Despite this, power has been largely ignored by the FPGA research community, whose prime focus to date has centered on improving FPGA speed and area-efficiency. This dissertation presents new techniques for optimizing and predicting the power consumption of FPGAs. First, two novel computer-aided design (CAD) techniques for FPGA leakage power reduction are presented. The proposed techniques are unique in that they substantially reduce leakage power, while imposing no cost, meaning that they have no impact on FPGA area-efficiency, speed, or fabrication cost. Following this, the circuit-level design of low-power FPGA interconnect is considered. A family of new low-power FPGA routing switches is proposed. The switches significantly reduce

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