Deterministic Boltzmann-transport solver has been integrated in performance analysis of logic cells. Employing universal-swing-factor (USF) approach, our setup accurately entails quasi-ballistic transport effects. The injection current and carrier mean free path (MFP) have been extracted for various channel dimensions and interface qualities. The resulting database is used to study candidate architecture for logic nodes. In particular, performance of ring oscillator (RO) with tapered FinFET is presented. For a given junction profile and contact-poly-pitch (CPP), the optimum gate-length (Lg), spacer thickness and contact-CD (CCD) are evaluated. The feasible gain by lowering the spacer k-value and contact resistance is also reported.