Exploiting dynamic reconfiguration of platform FPGAs: implementation issues

The effective use of dynamic reconfiguration requires the designer to address many implementation issues. The market introduction of feature-full platform FPGAs equipped with embedded CPU blocks expands the number of situations where dynamic reconfiguration may be applied to improve overall performance and logic utilization. The paper compares the design of two similar systems supporting dynamic reconfiguration and the issues that were addressed in their implementation. The first system supports 32-bit data transfers between CPU and the dynamically reconfigurable circuits. The other implementation supports 64-bit transfers, but its effective use is more complicated and several restrictions must be taken into account. The work includes a performance comparison of the two designs on several simple tasks, including pattern matching, image processing and hashing

[1]  Peter Sutton,et al.  JPG - a partial bitstream generation tool to support partial reconfiguration in virtex FPGAs , 2002, Proceedings 16th International Parallel and Distributed Processing Symposium.

[2]  Donald E. Eastlake,et al.  US Secure Hash Algorithm 1 (SHA1) , 2001, RFC.

[3]  Uri C. Weiser,et al.  Intel MMX for multimedia PCs , 1997, Commun. ACM.

[4]  J.C. Ferreira,et al.  Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems , 2007, IET Comput. Digit. Tech..

[5]  Fernando Gehm Moraes,et al.  PADReH - a framework for the design and implementation of dynamically and partially reconfigurable systems , 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).

[6]  Jürgen Becker,et al.  An FPGA run-time system for dynamical on-demand reconfiguration , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

[7]  João Canas Ferreira,et al.  Run-time reconfiguration support for FPGAs with embedded CPUs: the hardware layer , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

[8]  John W. Lockwood,et al.  Using PARBIT to Implement Partial Run-Time Reconfigurable Systems , 2002, FPL.

[9]  Adronis Niyonkuru,et al.  Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs , 2004, FPL.

[10]  Tobias Becker,et al.  Modular partial reconfigurable in Virtex FPGAs , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[11]  Hunter Scales,et al.  AltiVec Extension to PowerPC Accelerates Media Processing , 2000, IEEE Micro.