Run-Time Integration of Reconfigurable Video Processing Systems
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[1] Nachiket Kapre,et al. Packet Switched vs. Time Multiplexed FPGA Overlay Networks , 2006, 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.
[2] S. D. Haynes,et al. UltraSONIC: A Reconfigurable Architecture for Video Image Processing , 2002, FPL.
[3] N. Podhorszki,et al. Proceedings 10th Euromicro Workshop on Parallel, Distributed and Network-based Processing , 2002, Proceedings 10th Euromicro Workshop on Parallel, Distributed and Network-based Processing.
[4] Marco Platzner,et al. Synthesis of interfaces and communication in reconfigurable embedded systems , 2000 .
[5] Vincent John Mooney,et al. Automated bus generation for multiprocessor SoC design , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[6] Jeff Mason,et al. Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs , 2006, 2006 International Conference on Field Programmable Logic and Applications.
[7] Wayne Luk,et al. Video Image Processing with the Sonic Architecture , 2000, Computer.
[8] Vivek Sarkar,et al. Baring It All to Software: Raw Machines , 1997, Computer.
[9] Tobias Becker,et al. Modular dynamic reconfiguration in Virtex FPGAs , 2006 .
[10] Radu Marculescu,et al. On-chip traffic modeling and synthesis for MPEG-2 video applications , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[11] Sujit Dey,et al. Design space exploration for optimizing on-chip communication architectures , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[12] Russell Tessier,et al. An architecture and compiler for scalable on-chip communication , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[13] Ahmed Amine Jerraya,et al. Synthesis of system-level communication by an allocation-based approach , 1995, Proceedings of the Eighth International Symposium on System Synthesis.
[14] Ahmed Amine Jerraya,et al. Synthesis of system-level communication by an allocation-based approach , 1995 .
[15] Luca Benini,et al. Networks on Chips : A New SoC Paradigm , 2022 .
[16] Ulrich Rückert,et al. Dynamically reconfigurable system-on-programmable-chip , 2002, Proceedings 10th Euromicro Workshop on Parallel, Distributed and Network-based Processing.
[17] Manfred Glesner,et al. Bus-Based Communication Synthesis on System-Level , 1996, TODE.
[18] W. Dally,et al. Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[19] K. Keutzer,et al. System-level design: orthogonalization of concerns andplatform-based design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[20] Rudy Lauwereins,et al. Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs , 2002, FPL.
[21] Jürgen Teich,et al. A Dynamic NoC Approach for Communication in Reconfigurable Devices , 2004, FPL.
[22] Patrick Lysaght. FPGAs as meta-platforms for embedded systems , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..
[23] Grant Martin,et al. Surviving the SOC Revolution: A Guide to Platform-Based Design , 1999 .
[24] Wayne Luk,et al. A Structured Methodology for System-on-an-FPGA Design , 2004, FPL.