A Dynamic Greedy Test Scheduler for Optimizing Probe Motion in In-Circuit Testers

The test of a printed-circuit board assembly often includes in-circuit test, which mainly aims at checking whether the different components have been correctly soldered. A tester may adopt either the bed of nails, or the flying probes architecture. In the latter case, probes move to contact test points on each side of the board to perform the required tests. In order to minimize the test time, the sequence of movements of the probes should be optimized, taking into account the tester capabilities, the board layout, and the several constraints coming from the environment and the customer. In this paper we describe the approach developed for optimizing tests on the SPEA 4080, which exploits the new hardware available to combine reduced test time with short test-generation time. Experimental results show the effectiveness of the proposed solution.