Ultra-low voltage CMOS current-mode four-quadrant multiplier

A novel configuration of a four-quadrant current multiplier is introduced in this paper. The realisation is achieved through the utilisation of the voltage translinear principle; the derived topology simultaneously offers the attractive benefits of ultra-low voltage operation and reduced DC power dissipation, in comparison with the corresponding already published multipliers. The above have been achieved without increasing the circuit complexity. The behaviour of the multiplier has been evaluated through simulation results, using the Analog Design Environment and the design kit provided by the Taiwan Semiconductor Manufacturing Company 180 nm complementary metal-oxide semiconductor process.