A robust repair-aware test method for multi-memory

A complex SoC typically consists of numerous of memories in today's digital systems. This paper presents a test/repair structure based on memory grouping strategy and a revised distributed BIST structure for complex SoC devices. A gated selecting method is added to the distributed BIST structure. Also, it can be used to a robust post repair stage based on BIRA and memory grouping in test flow to improve the test coverage. Simulation results by mathematical method show that the proposed test flow has achieved a significant increase in yield of memories.

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