A programmable 80ns 1Mb CMOS EPROM

CONTINUING DEMANDS for high-speed, low-power and highdensity EPROMs are being created by the evolution of high performance computer systems. This paper will describe an asynchronous lMb CMOS EPROM with both word and byte operation modes’. An Address Transition Detector (.4TD), MidWord-Line Buffer (MWLB) and sensing are utilized to realize an 80ns access time. Programming of 2Ops/word has been realized by introducing selective DSA (Diffused Self-Align) structure into the memory cell transistor. The CMOS circuit and automatic power down function result in 50mW operating power and subPW standby power.

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