C-Element model for SET fault emulation

Single Event Transients (SETs) are a concern in digital circuits using nanometric technologies. Proposed solutions include the insertion of pulse filtering cells in the circuit, like some C-Element based cells. These filters are usually introduced at flip-flop inputs. In general, protecting every flip-flop with SET filters is a very costly solution in terms of area. Selective hardening of critical elements is considered a wiser solution. Even if there are already emulation based techniques able to predict the SET error rate and determine the critical parts of a circuit, there is no reasonable way to evaluate the circuit robustness after the insertion of SET filtering structures. In this paper, a SET filter cell has been modeled in order to be included in a FPGA fault injection system. Results show that it is feasible to compare the circuit robustness before and after hardening, and close the loop at the design stage, before proceeding to radiation tests.