Exponentially tapered H-tree clock distribution networks

Exponentially tapered interconnect can reduce the dynamic power dissipation of clock distribution networks. A criterion for sizing H-tree clock networks is proposed. The technique reduces the power dissipated by an example clock network by up to 12% while preserving the signal transition times and propagation delays. Furthermore, the inductive behavior of the interconnects is reduced, decreasing the inductive noise. Exponentially tapered interconnects reduce by approximately 20% the difference between the overshoots in the signal at the input of a tree as compared to a uniform tree with the same area overhead.

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