Modeling of the Influence of Graded Element Matching Errors in CMOS Current-Steering DACs

In analog and mixed-mode circuits the matching between circuit elements is crucial.For example, in binary encoded digital-to-analog converters (DACs) the matchingbetween different bit weights can set the limit on the performance. Related to earlier workmodeling the influence of stochastic matching, the influence of graded element matching errorson the performance of current-steering DACs is shown. Presented are calculated results thatcorrelate very well with simulated results. As performance measures we use both static measuresas DNL and INL as well as frequency domain parameters as SNDR and SFDR. This discussioncan also be applied to other DAC structures, for example switched-capacitor.