An Efficient and Extendable Modeling Approach for VLIW DSP Processors

This paper presents an efficient and extendable modeling approach for DSP processors with VLIW architecture. The proposed approach is designed for sequential implementation platforms such as C++ programming language. It employs specific pipeline modeling technique called reverse calling. As a sample implementation, a DSP processor model is designed based on Texas Instruments (TI) C62xx architecture. The processor model handles pipeline resources (memories and register files) during concurrent accesses by updating method. To verify the functionality of the model, a cycle-accurate simulation environment is developed using C++ programming language. In this simulator, a DSP-specific data type, called DSPDT, is designed and implemented for bit-accurate implementation of signal processing operations. The simulation environment utilizes a simple assertion-based verification technique with messages using three levels of severities: Alert, Warning, and Error. The simulator is functionally validated by practical DSP benchmarks such as IIR filters, correlation, FFT blocks and also the G.729a speech codec for single and multiple speech channels.