Simultaneous topology selection and sizing for synthesis of analog cells

In this paper, an optimization-based synthesis method for analog integrated circuits is proposed, which employs the simulated annealing algorithm (SA) to do topology selection and sizing simultaneously. This approach overcomes the shortage of the traditional two-step synthesis mode. Moreover, an iteration strategy is composed to reduce the computational cost of SA. Taking this methodology, a synthesizer is developed which performs well in synthesizing many analog IC cells, such as simple amplifiers, current mirrors, operational amplifiers (OP Amp), analog multipliers, etc.