Techniques to Extend Canary-Based Standby $V_{DD}$ Scaling for SRAMs to 45 nm and Beyond

VDD scaling is an efficient technique to reduce SRAM leakage power during standby mode. The data retention voltage (DRV) defines the minimum VDD that can be applied to an SRAM cell without losing data. The conventional worst-case guard-banding approach selects a fixed standby supply voltage at design time to accommodate the variability of DRV, which sacrifices potential power savings for non-worst-case scenarios. We have proposed a canary-based feedback to achieve aggressive power savings by tracking PVT variations through canary cell failures. In this paper, we show new measured silicon results that confirm the ability of the canary scheme to track PVT changes. We thoroughly analyze the adaptiveness of the canary cells for tracking changes in the SRAM array, including the ability to track PVT fluctuations. We present circuits for robustly building the control logic that implements the feedback mechanism at subthreshold supply voltages, and we derive a new analytical model to help tune the canary cells in the presence of variations. To realistically quantify the potential savings achievable by the canary scheme, we assess the impact of various sources of overhead. Finally, we investigate the performance of the canary based scheme in nanometer technologies, and we show that it promises to provide substantial standby power savings down to the 22 nm node.

[1]  Jan M. Rabaey,et al.  SRAM leakage suppression by minimizing standby supply voltage , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

[2]  A. Alvandpour,et al.  High–performance, low–power, and leakage–tolerance challenges for sub–70nm microprocessor circuits , 2002, Proceedings of the 28th European Solid-State Circuits Conference.

[3]  D. Blaauw,et al.  Single-V/sub DD/ and single-V/sub T/ super-drowsy techniques for low-leakage high-performance instruction caches , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[4]  Kaushik Roy,et al.  Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[5]  Jiajing Wang,et al.  Canary Replica Feedback for Near-DRV Standby VDD Scaling in a 90nm SRAM , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[6]  A.P. Chandrakasan,et al.  Voltage Scalable Switched Capacitor DC-DC Converter for Ultra-Low-Power On-Chip Applications , 2007, 2007 IEEE Power Electronics Specialists Conference.

[7]  N. Vallepalli,et al.  SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction , 2005, IEEE Journal of Solid-State Circuits.

[8]  Yu Cao,et al.  New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[9]  Steven K. Hsu,et al.  High-performance low-power microprocessor circuits , 2001 .

[10]  Rob A. Rutenbar,et al.  Statistical Blockade: A Novel Method for Very Fast Monte Carlo Simulation of Rare Circuit Events, and its Application , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[11]  Atila Alvandpour,et al.  High–performance, low–power, and leakage–tolerance challenges for sub–70nm microprocessor circuits , 2002 .

[12]  L.T. Clark,et al.  Reverse-body bias and supply collapse for low effective standby power , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Jiajing Wang,et al.  Statistical modeling for the minimum standby supply voltage of a full SRAM array , 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.