Time-domain analog-to-digital converters with domino delay lines

A time-domain analog-to-digital (ADC) based on a domino delay line for high-speed applications is presented. The structure is mainly built on digital blocks and is compatible with digital nanometer processes. The domino delay line consists of enhanced delay units and parallel reset for reducing the propagation delay. Dual-mode operation including a Nyquist mode and a sigma-delta modulation (SDM) mode can be provided by different processing of residue phases. Furthermore, a digital calibration technique is also proposed to compensate the inherently nonlinear behaviors. The proposed structure has been designed and implemented in a 0.18-μm standard CMOS process with active area of 0.01 mm2. Same design is also ported and simulated in 90-nm, and 55-nm CMOS process, respectively. The figure-of-merit (FOM) of these ADCs can achieve 1.65, 0.28, and 0.07 pJ/Conversion-Step.

[1]  A. K. Gupta,et al.  A Two-Stage ADC Architecture With VCO-Based Second Stage , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  R.W. Dutton,et al.  Impact of Scaling on Analog Performance and Associated Modeling Needs , 2006, IEEE Transactions on Electron Devices.

[3]  Y. Makino,et al.  An all-digital analog-to-digital converter with 12-μV/LSB using moving-average filtering , 2003, IEEE J. Solid State Circuits.

[4]  M. Elmasry,et al.  A 6-Bit 1.6-GS/sLow-Power Wideband Flash ADC Converter in 0.13-µm CMOS Technology , 2008, IEEE J. Solid State Circuits.

[5]  Shen-Iuan Liu,et al.  An 8-bit 20-MS/s ZCBC Time-Domain Analog-to-Digital Data Converter , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  Edgar Sánchez-Sinencio,et al.  A Continuous Time Multi-Bit $\Delta \Sigma$ ADC Using Time Domain Quantizer and Feedback Element , 2011, IEEE Journal of Solid-State Circuits.

[7]  B.P. Ginsburg,et al.  500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC , 2007, IEEE Journal of Solid-State Circuits.

[8]  M.Z. Straayer,et al.  A 12-Bit, 10-MHz Bandwidth, Continuous-Time $\Sigma\Delta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer , 2008, IEEE Journal of Solid-State Circuits.

[9]  B. Nauta,et al.  Analog circuits in ultra-deep-submicron CMOS , 2005, IEEE Journal of Solid-State Circuits.