Extracting power supply current profile by using interposer-based low-noise probing technique for PDN design of high-density POP

Firmly understanding the power supply current profile (PSCP) of various scenarios used in real use cases is essential for the simulation and design of power delivery network (PDN) of system-on-chip (SOC) to maximize processor’s performance within limited cost budget for die, package, and system, because the low power hard-ware implementation of leading-edge SOC including high performance computing cores for video data processing, 3D graphics, augmented reality, artificial intelligence, and 5G data communication with battery powered portable electronic devices, whose primary concern is the low power consumption, has been concentrated on reducing the minimum allowable power supply voltage for high performance computing cores including CPU, GPU, NPU and CP. The objective of this work is presenting the method to precisely probe power supply voltage fluctuation (PSVF) of whole power domains for power supply current profile (PSCP) extraction of entire cores, for which the authors present an concrete analysis methodology, based on which a test interposer scheme targeted for probing core logic blocks at the proper position of PDN is implemented and demonstrated when in operation. The proposed low noise probing system for acquiring PSCP is constructed by a test interposer designed with rigorous PI analyses.

[1]  Dan Oh,et al.  Power integrity analysis for core logic blocks , 2013, 2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems.

[2]  Dan Oh,et al.  Power integrity analysis for core timing models , 2014, 2014 IEEE International Symposium on Electromagnetic Compatibility (EMC).

[3]  Ramachandra Achar,et al.  Fast Analysis of Time Interval Error in Current-Mode Drivers , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Malgorzata Marek-Sadowska,et al.  Buffer delay change in the presence of power and ground noise , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[5]  I. Kantorovich,et al.  Measurement of worst-case power delivery noise on chip under operating conditions , 2006, 2006 IEEE Workship on Signal Propagation on Interconnects.

[6]  Jisoo Hwang,et al.  A New SI-PI co-Simulation Approach for Efficient Consideration of Coupling Between PDN and SDN , 2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC).

[7]  Jai Narayan Tripathi,et al.  A Review on Power Supply Induced Jitter , 2019, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[8]  Ramachandra Achar,et al.  Efficient Modeling of Power Supply Induced Jitter in Voltage-Mode Drivers (EMPSIJ) , 2017, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[9]  Joungho Kim,et al.  Power distribution networks for system-on-package: status and challenges , 2004, IEEE Transactions on Advanced Packaging.

[10]  Ramachandra Achar,et al.  Analysis of Jitter for a Chain-of-Inverters including On-chip Interconnects , 2019, 2019 IEEE 23rd Workshop on Signal and Power Integrity (SPI).

[11]  Jordi Cortadella,et al.  Voltage Noise Analysis with Ring Oscillator Clocks , 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

[12]  Tad Kwasniewski,et al.  Propagation Delay-Based Expression of Power Supply-Induced Jitter Sensitivity for CMOS Buffer Chain , 2016, IEEE Transactions on Electromagnetic Compatibility.

[13]  Sachin S. Sapatnekar,et al.  Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors , 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

[14]  Jingook Kim,et al.  Analytical jitter estimation of two-stage output buffers with supply voltage fluctuations , 2014, 2014 IEEE International Symposium on Electromagnetic Compatibility (EMC).

[15]  Kenji Araki,et al.  Improved Target Impedance for Power Distribution Network Design With Power Traces Based on Rigorous Transient Analysis in a Handheld Device , 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[16]  Aida Todri,et al.  A Study of 3-D Power Delivery Networks With Multiple Clock Domains , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  I. Kantorovich,et al.  Effectiveness of on-die decoupling capacitance in improving chip performance , 2008, 2008 IEEE-EPEP Electrical Performance of Electronic Packaging.

[18]  Masanori Hashimoto,et al.  A Frequency-Dependent Target Impedance Method Fulfilling Both Average and Dynamic Voltage Drop Constraints , 2019, 2019 IEEE 23rd Workshop on Signal and Power Integrity (SPI).

[19]  Heeseok Lee,et al.  Power Delivery Network Design for 3D SIP Integrated over Silicon Interposer Platform , 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

[20]  Ramachandra Achar,et al.  A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers , 2019, IEEE Access.

[21]  Jing Wang,et al.  A vector-based approach for power supply noise analysis in test compaction , 2005, IEEE International Conference on Test, 2005..

[22]  Li Zheng,et al.  Full-Chip Power Supply Noise Time-Domain Numerical Modeling and Analysis for Single and Stacked ICs , 2016, IEEE Transactions on Electron Devices.

[23]  Giovanni De Micheli,et al.  The combined effect of process variations and power supply noise on clock skew and jitter , 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

[24]  Gang Huang,et al.  Physical Model for Power Supply Noise and Chip/Package Co-Design in Gigascale Systems with the Consideration of Hot Spots , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[25]  Dan Oh,et al.  Improving the target impedance method for PCB decoupling of core power , 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

[26]  S. Moon,et al.  Design and Analysis of MIM Capacitor on Power Integrity Effects for HPC and Network Applications , 2019, 2019 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI).

[27]  Joungho Kim,et al.  Signal Integrity Design and Analysis of a Multilayer Test Interposer for LPDDR4 Memory Test With Silicone Rubber-Based Sheet Contact , 2017, IEEE Transactions on Electromagnetic Compatibility.

[28]  A. Waizman,et al.  CPU Power Delivery Impedance Profile Resonances Impact on Core FMAX , 2006, 2006 IEEE Electrical Performane of Electronic Packaging.

[29]  Seungki Nam,et al.  An Approach for PDN Simplification of a Mobile Processor , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[30]  M. Swaminathan,et al.  Impact of power-supply noise on timing in high-frequency microprocessors , 2002, Electrical Performance of Electronic Packaging,.

[31]  Jun Fan,et al.  Precise Analytical Model of Power Supply Induced Jitter Transfer Function at Inverter Chains , 2018, IEEE Transactions on Electromagnetic Compatibility.

[32]  T. Strach,et al.  Estimating the First Voltage Drop for ICs with leakage , 2006, 2006 IEEE Workship on Signal Propagation on Interconnects.

[33]  I. Kantorovich,et al.  Maximum Tolerable Power Supply Noise for Data-Clock Synchronization , 2006, 2006 IEEE Electrical Performane of Electronic Packaging.

[34]  Dan Oh,et al.  System Level Modeling of Timing Margin Loss Due to Dynamic Supply Noise for High-Speed Clock Forwarding Interface , 2016, IEEE Transactions on Electromagnetic Compatibility.

[35]  Jun Fan,et al.  Modeling of power supply induced jitter (PSIJ) transfer function at inverter chains , 2017, 2017 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI).

[36]  Paolo A. Aseron,et al.  Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency , 2010, IEEE Custom Integrated Circuits Conference 2010.

[37]  T. Rahal-Arabi,et al.  Enhancing microprocessor immunity to power supply noise with clock-data compensation , 2006, IEEE Journal of Solid-State Circuits.