The successive approximation register (SAR) ADC is the most energy efficient architecture with moderate conversion rate and resolution. However, its comparator noise limits its resolution without sacrificing power efficiency. The delta-sigma modulator (DSM) is the most popular architecture for achieving high SNDR due to its oversampling, but the bulky operational amplifier (op-amp) makes it area inefficient. In LTE Advanced, the bandwidth (BW) of downlink ADCs needs to be configured according to the number of inter-band non-contiguous carrier aggregation (NCCA), which motivates us to combine the benefits of both architectures to reduce area and power consumption simultaneously with high SNDR. The noise-shaping SAR ADC [1] suppresses the comparison and quantization noise in signal BW using a simple cascaded FIR-IIR filter, which obviates the need for a power-hungry low-noise comparator or high-performance op-amp. To some extent, the noise-shaping SAR ADC is a hybrid of DSM and SAR ADCs. Hence, it has the potential to achieve the high resolution and good power efficiency of DSM and SAR ADCs, respectively. However, the passive sampling in an FIR filter introduces considerable thermal noise to the ADC, making it difficult to achieve a high SNR. This work presents an energy-efficient noise-shaping SAR ADC that uses a gain-enhanced dynamic amplifier and some capacitors to construct a low-noise dynamic FIR-IIR filter. The prototype achieves a peak SNDR of 79.74dB over a 5MHz BW with a power consumption of 0.46mW from a 1V supply.
[1]
Akira Matsuzawa,et al.
A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique
,
2011,
2011 IEEE International Symposium of Circuits and Systems (ISCAS).
[2]
Han Yan,et al.
11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS
,
2014,
2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).
[3]
Guowen Wei,et al.
A 13-ENOB, 5 MHz BW, 3.16 mW multi-bit continuous-time ΔΣ ADC in 28 nm CMOS with excess-loop-delay compensation embedded in SAR quantizer
,
2015,
2015 Symposium on VLSI Circuits (VLSI Circuits).
[4]
P. Cochat,et al.
Et al
,
2008,
Archives de pediatrie : organe officiel de la Societe francaise de pediatrie.
[5]
Hsin-Shu Chen,et al.
11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS
,
2014,
2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).
[6]
Nan Sun,et al.
Predicting ADC: A new approach for low power ADC design
,
2014,
2014 IEEE Dallas Circuits and Systems Conference (DCAS).
[7]
Michael P. Flynn,et al.
A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC
,
2012,
IEEE Journal of Solid-State Circuits.