A 4.92-5.845 GHz direct-conversion CMOS transceiver for IEEE 802.11a wireless LAN

A fully integrated CMOS direct-conversion 5 GHz transceiver is implemented in a 0.18 /spl mu/m digital CMOS process and housed in an LPCC-48 package. This chip, along with a companion baseband chip, provides a complete 802.11a solution covering all of the world-wide 4.92-5.845 GHz bands. The receiver achieves a 3.5 dB NF while the transmitter achieves a +23 dBm saturated output power. The integrated PA utilizes a linearization technique to allow for high efficiency while maintaining the linear operation required by QAM64 OFDM signals. The transceiver achieves low cost and high yield through the use of various integrated self-contained or system level calibration techniques.

[1]  Ran-Hong Yan,et al.  5 GHz CMOS radio transceiver front-end chipset , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[2]  H.R. Rategh,et al.  A 5-GHz CMOS wireless LAN receiver front end , 2000, IEEE Journal of Solid-State Circuits.

[3]  M. Zargari,et al.  A 5 GHz CMOS transceiver for IEEE 802.11a wireless LAN , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[4]  Ahmadreza Rofougaran,et al.  A 5-GHz direct-conversion CMOS transceiver utilizing automatic frequency control for the IEEE 802.11a wireless LAN standard , 2003, IEEE J. Solid State Circuits.

[5]  Bruce A. Wooley,et al.  A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems , 2002 .

[6]  Pengfei Zhang,et al.  A direct conversion CMOS transceiver for IEEE 802.11a WLANs , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..