Invasive Algorithms and Architectures Invasive Algorithmen und Architekturen

Abstract In this seminal paper, we introduce the notion of invasive algorithms and corresponding parallel computing architectures also called invasive. The main idea of invasion is to add to a given single-processor program the ability to explore neighbor processors and to copy itself to such processors in a phase of invasion, and then to execute the given problem in parallel based on the available (invasible) region on a given multi-processor architecture. After this parallel execution, the program may perform a retreat and resume execution again sequentially on the single processor. In order to support invasion, new architectural concepts as well as means to support invasion on reconfigurable MPSoCs are provided. We do believe that invasion will become an important step towards self-organizing behavior which will be needed in the massively parallel MPSoC area beyond the year 2020 with unrivaled performance and resource efficiency numbers as one of the main challenges for MPSoCs apart from their programming. In case of invasion, an algorithm is able to spread itself for parallel execution based on availability of processing resources.

[1]  Jürgen Teich,et al.  A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing , 2006, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06).

[2]  Paul Feautrier,et al.  Automatic Parallelization in the Polytope Model , 1996, The Data Parallel Programming Model.

[3]  Nikil Dutt,et al.  Processor description languages : applications and methodologies , 2008 .

[4]  Olivier Temam,et al.  CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[5]  Jürgen Teich,et al.  Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology , 2006, Int. J. Embed. Syst..

[6]  Jürgen Becker,et al.  New Adaptive Multi-grained Hardware Architecture for Processing of Dynamic Function Patterns (Neue adaptive multi-granulare Hardwarearchitektur) , 2007, it Inf. Technol..

[7]  Jürgen Teich,et al.  A practical approach for circuit routing on dynamic reconfigurable devices , 2005, 16th IEEE International Workshop on Rapid System Prototyping (RSP'05).

[8]  Jürgen Teich,et al.  Reconfigurable Computing Systems (Rekonfigurierbare Rechensysteme) , 2007, it Inf. Technol..

[9]  Jürgen Teich,et al.  A Dynamic NoC Approach for Communication in Reconfigurable Devices , 2004, FPL.

[10]  Jürgen Teich,et al.  A highly parameterizable parallel processor array architecture , 2006, 2006 IEEE International Conference on Field Programmable Technology.

[11]  Axel Jantsch,et al.  Network on Chip : An architecture for billion transistor era , 2000 .

[12]  Jürgen Teich,et al.  DyNoC: A dynamic infrastructure for communication in dynamically reconfugurable devices , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[13]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[14]  Jürgen Teich,et al.  The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer , 2007, J. VLSI Signal Process..

[15]  Dietmar Fey,et al.  Marching-pixels: a new organic computing paradigm for smart sensor processor arrays , 2005, CF '05.

[16]  Wolfgang Rosenstiel,et al.  Organic Computing at the System on Chip Level , 2006, 2006 IFIP International Conference on Very Large Scale Integration.

[17]  Jürgen Teich,et al.  Resource constrained and speculative scheduling of an algorithm class with run-time dependent conditionals , 2004 .

[18]  Benjamin Satzger,et al.  Adaptive Self-optimization in Distributed Dynamic Environments , 2007, First International Conference on Self-Adaptive and Self-Organizing Systems (SASO 2007).