Low-cost, on-line self-testing of processor cores based on embedded software routines

Abstract On-line testing for complex system-on-chip architectures requires a synergy of concurrent and non-concurrent fault detection mechanisms. While concurrent fault detection is mainly achieved by hardware or software redundancy, like duplication, non-concurrent fault detection, particularly useful for periodic testing, is usually achieved through hardware-based self-test. Software-based self-test has been recently proposed as an effective alternative to hardware-based self-test allowing at-speed testing while eliminating area, performance and power consumption overheads. In this paper, we investigate the applicability of software-based self-test to non-concurrent on-line testing of embedded processor cores and define, for the first time, the corresponding requirements. Low-cost, in-field testing requirements, particularly small test execution time and low power consumption guide the development of self-test routines. We show how self-test programs with a limited number of memory references and based on compact test routines provide an efficient low-cost on-line test strategy for an RISC processor core.