Net Balanced Floorplanning Based on Elastic Energy Model

Floorplanning is becoming more and more important in VLSI design flows, especially for system-on-chip (SoC) designs where IP blocks dominate standard cells. Moreover, in deep sub-micron technologies, where process variations can introduce extra signal skew, it is desirable to have floorplans with balanced net delays to increase the safety margins of the design. In this paper, we investigate the properties of floorplanning based on the elastic energy model. The B*-tree, which is based on an ordered binary tree, is used for circuit representation and the elastic energy is used as the cost function. To evaluate how well a net is balanced, we introduced a new metric 'unbalancing'. A more balanced net would have a smaller 'unbalancing' value. Experimental results show that our approach can not only meet fixed-outline constraints, but also achieve significant improvements in net balance for all the circuits in the MCNC benchmark.

[1]  R. Otten.  Automatic Floorplan Design , 1982, DAC 1982.

[2]  Yao-Wen Chang,et al.  Multilevel floorplanning/placement for large-scale modules using B*-trees , 2003, DAC '03.

[3]  Igor L. Markov,et al.  Fixed-outline floorplanning through better local search , 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

[4]  Yoji Kajitani,et al.  An enhanced Q-sequence augmented with empty-room-insertion and parenthesis trees , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[5]  Kevin Skadron,et al.  A Case for Thermal-Aware Floorplanning at the Microarchitectural Level , 2005, J. Instr. Level Parallelism.

[6]  Kia Bazargan,et al.  Microarchitecture floorplanning for sub-threshold leakage reduction , 2007 .

[7]  Yao-Wen Chang,et al.  TCG: a transitive closure graph-based representation for non-slicing floorplans , 2001, DAC '01.

[8]  Srinivas Katkoori,et al.  Energy model based macrocell placement for wirelength minimization , 2004, 17th International Conference on VLSI Design. Proceedings..

[9]  Evangeline F. Y. Young,et al.  Optimizing wirelength and routability by searching alternative packings in floorplanning , 2008, TODE.

[10]  H. Murata,et al.  Rectangle-packing-based module placement , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[11]  Robert K. Brayton,et al.  A force-directed macro-cell placer , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[12]  Hai Zhou,et al.  ACG-adjacent constraint graph for general floorplans , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[13]  Yao-Wen Chang,et al.  B*-trees: a new representation for non-slicing floorplans , 2000, Proceedings 37th Design Automation Conference.

[14]  Srinivas Katkoori,et al.  Net-based force-directed macrocell placement for wirelength optimization , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[15]  Jarrod A. Roy,et al.  Min-cut floorplacement , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Yici Cai,et al.  Corner block list: an effective and efficient topological representation of non-slicing floorplan , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[17]  Takeshi Yoshimura,et al.  An O-tree representation of non-slicing floorplan and its applications , 1999, DAC '99.

[18]  Sachin S. Sapatnekar,et al.  Temperature-Aware Floorplanning of Microarchitecture Blocks with IPC-Power Dependence Modeling and Transient Analysis , 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.