A Reconfigurable Architecture to Implement Linear Transforms of Image Processing Applications
暂无分享,去创建一个
[1] Stephan Wong,et al. A New Approach to Implement Discrete Wavelet Transform Using Collaboration of Reconfigurable Elements , 2009, 2009 International Conference on Reconfigurable Computing and FPGAs.
[2] Roberto Guerrieri,et al. A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing , 2010, IEEE Journal of Solid-State Circuits.
[3] Martin Margala,et al. Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[4] Li Li,et al. An improved FFT architecture optimized for reconfigurable application specified processor , 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).
[5] Amitabha Sinha,et al. A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays , 2013, CARN.
[6] Swapan Kumar Samaddar. A generalized architecture for linear transform , 2013 .
[7] Mingyu Wang,et al. A pipelined area-efficient and high-speed reconfigurable processor for floating-point FFT/IFFT and DCT/IDCT computations , 2016, Microelectron. J..
[8] T. Vigneswaran,et al. Reconfigurable FFT Processor - A Broader Perspective Survey , 2013 .
[9] Shanq-Jang Ruan,et al. A computationally efficient high-quality cordic based DCT , 2006, 2006 14th European Signal Processing Conference.
[10] Liang-Gee Chen,et al. Reconfigurable discrete cosine transform processor for object-based video signal processing , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).
[11] A. Sanyal,et al. A Combined Architecture for FDCT Algorithm , 2012, 2012 Third International Conference on Computer and Communication Technology.
[12] Liang-Gee Chen,et al. Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems , 2005, J. VLSI Signal Process..
[13] Wolfgang Fengler,et al. A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor , 2019, Int. J. Reconfigurable Comput..
[14] Suresh Mopuri,et al. A Reconfigurable High Speed Architecture Design for Discrete Hilbert Transform , 2014, IEEE Signal Processing Letters.
[15] Uma Rajaram. Design of fir filter for adaptive noise cancellation using context switching reconfigurable EHW architecture , 2009 .
[16] S SrivatsavaP,et al. Reconfigurable MDC Architecture Based FFT Processor , 2014 .
[17] Narsingh Deo,et al. Graph Theory with Applications to Engineering and Computer Science , 1975, Networks.
[18] Alexander Petrovsky,et al. Dynamic Reconfigurable on the Lifting Steps Wavelet Packet Processor with Frame-Based Psychoacoustic Optimized Time- Frequency Tiling for Real-Time Audio Applications , 2013 .
[19] Vinita Vasudevan,et al. Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.