Probabilistic Error Propagation through Approximated Boolean Networks
暂无分享,去创建一个
[1] Yi Wu,et al. Approximate logic synthesis for FPGA by wire removal and local function change , 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).
[2] Muhammad Shafique,et al. Compiler-driven error analysis for designing approximate accelerators , 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[3] Jason Cong,et al. On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping , 1993, 30th ACM/IEEE Design Automation Conference.
[4] Jürgen Teich,et al. Design Space Exploration of Multi-output Logic Function Approximations , 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[5] John Lach,et al. A methodology for energy-quality tradeoff using imprecise hardware , 2012, DAC Design Automation Conference 2012.
[6] Sabrina Hirsch,et al. Logic Minimization Algorithms For Vlsi Synthesis , 2016 .
[7] John Sartori,et al. Statistical analysis and modeling for error composition in approximate computation circuits , 2013, 2013 IEEE 31st International Conference on Computer Design (ICCD).
[8] Jürgen Teich,et al. Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders , 2018, IEEE Embedded Systems Letters.
[9] Wei Luo,et al. Joint precision optimization and high level synthesis for approximate computing , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).
[10] Alberto L. Sangiovanni-Vincentelli,et al. Multiple-Valued Minimization for PLA Optimization , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[11] Yi Wu,et al. An efficient method for multi-level approximate logic synthesis under error rate constraint , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).
[12] Weikang Qian,et al. DALS: Delay-driven Approximate Logic Synthesis , 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[13] Rolf Drechsler,et al. BDD minimization for approximate computing , 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).
[14] Robert K. Brayton,et al. SAT-based complete don't-care computation for network optimization , 2005, Design, Automation and Test in Europe.
[15] L. H. Goldstein,et al. SCOAP: Sandia Controllability/Observability Analysis Program , 1980, 17th Design Automation Conference.
[16] Yi Wu,et al. Efficient Batch Statistical Error Estimation for Iterative Multi-level Approximate Logic Synthesis , 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).
[17] Andreas Gerstlauer,et al. Statistical quality modeling of approximate hardware , 2016, 2016 17th International Symposium on Quality Electronic Design (ISQED).
[18] Zainalabedin Navabi. Digital System Test and Testable Design: Using HDL Models and Architectures , 2010 .