A user configurable gate array using CMOS-EPROM technology

A 68-pin programmable gate array, implemented in 1- mu m CMOS-EPROM technology, is described. Input-to-output delay of 20 ns for single-level logic is achieved for an array of 258 input lines X 199 product terms. Architecture with 96 NAND foldbacks allows multilevel logic capability. The die size is 55.3 Kmil/sup 2/, and a power-down option is provided. In addition to the main array there is a clock array which generates 10 internal clocks for 10 of the buried JK flip-flops. A scan mode is implemented to offer additional testability of the flip-flops.<<ETX>>

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