论文信息 - Low-power logic styles for full-adder circuits

Low-power logic styles for full-adder circuits

This paper contributes to a better knowledge of the behaviour of conventional CMOS and CPL full-adder circuits when low voltage, low power or small power-delay products are of concern. It completes and overcomes limitations of previous studies as optimal power-delay curves, for CPL and CMOS full adders, have been constructed using an automatic sizing tool based on statistical optimization. Supply voltages of 3.3 V and 1.5 V have been considered. This study shows that full adders with minimum power consumption are accessible by using the conventional CMOS design style. As a counterpart, minimum delay full adders are obtained with CPL.

J.M. Quintana | E. Rodriguez-Villegas | M.J. Avedillo | R. Jimenez

[1] C. Piguet,et al. Technology- and power-supply-independent cell library , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[2] F. J. Kratochvil. A 0.25-μm CMOS 0.9-V 100-MHz DSP Core , 1997 .

[3] Mohamed I. Elmasry,et al. Circuit techniques for CMOS low-power high-performance multipliers , 1996 .

[4] Tohru Mogami,et al. A 0.25-/spl mu/m CMOS 0.9-V 100-MHz DSP core , 1997 .

[5] A. Rodríguez-Vázquez,et al. Global design of analog cells using statistical optimization techniques , 1994 .

[6] Haomin Wu,et al. A new design of the CMOS full adder , 1992 .

[7] Neil Weste,et al. Principles of CMOS VLSI Design , 1985 .

[8] Takayasu Sakurai,et al. A swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications , 1996, IEEE J. Solid State Circuits.

[9] Yasuhiko Sasaki,et al. Top-down pass-transistor logic design , 1996, IEEE J. Solid State Circuits.

[10] Wolfgang Fichtner,et al. Low-power logic styles: CMOS versus pass-transistor logic , 1997, IEEE J. Solid State Circuits.

[11] Anantha P. Chandrakasan,et al. Low Power Digital CMOS Design , 1995 .