Regular Versus Irregular TSV Placement for 3D IC

Through-silicon via (TSV) is the enabling technology for fine-grained integration of multiple dies into a single 3D stack. However, TSVs occupy significant silicon area due to their sheer size, which has a great effect on the power and performance of 3D ICs. Whereas well-managed TSVs alleviate routing congestion, reduce wirelength, and improve performance, excessive or ill-managed TSVs not only increase the die area but also degrade performance and power. In this chapter, we study the impact of TSVs on the quality of 3D IC layouts. We first study two design schemes, namely TSV co-placement (irregular TSV placement) and TSV site (regular TSV placement), for the design of 3D ICs. In addition, we develop a force-directed 3D gate-level placement algorithm to find optimal locations of TSVs and gates. One key problem to solve in regular TSV placement is how to assign 3D nets to pre-placed TSVs. To solve this problem effectively, we study two TSV assignment algorithms, compare them with other TSV assignment algorithms, and analyze the impact of the quality of TSV assignment algorithms on 3D ICs. Experimental results show that the wirelength of 3D ICs is shorter than that of 2D ICs by up to 25 %. We also compare timing and power of 2D and 3D ICs.

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