A sensitivity driven 10T SRAM cell to mitigate process variation via selective back-gate biasing

Process variation is become future design challenge in ultra scaled identically designed Static Random Access Memory (SRAM), hence amendment in SRAM is needed. In this paper, we propose a novel low-power sensitivity-driven and inter-die process variation aware 10T SRAM cell via selective back-gate (SBG) biasing technique with independent-double-gate FinFET. As driver and load are the latching transistor in SRAM cell, where stability of cell depends on them, therefore SBG is applied on these transistors. SBG improves design yield and reduces parametric failures of proposed 10T cell by exploiting controlled conductivity of these transistors using back-gate biasing. Simulation results show that proposed SRAM cell improves write margin, static noise margin and read noise margins by 76%, 30% and 22%, respectively along with improved performance.

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