ESD Protection Design for Mixed-Voltage I/O Interfaces -- Overview

Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. This paper presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. The ESD design constraints in mixed-voltage I/O interfaces, the classification, and analysis of ESD protection designs for mixed-voltage I/O interfaces are presented and discussed.

[1]  Ming-Dou Ker,et al.  Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-/spl mu/m CMOS technology , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[2]  D. B. Krakauer,et al.  ESD protection for mixed-voltage I/O using NMOS transistors stacked in a cascode configuration , 1998 .

[3]  G. P. Singh,et al.  High-voltage-tolerant I/O buffers with low-voltage CMOS process , 1999, IEEE J. Solid State Circuits.

[4]  V.A. Vashchenko,et al.  Physical limitation of the cascoded snapback NMOS ESD protection capability due to the non-uniform turn-off , 2004, IEEE Transactions on Device and Materials Reliability.

[5]  Timothy J. Maloney,et al.  Novel clamp circuits for IC power supply protection , 1995 .

[6]  Ming-Dou Ker,et al.  Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers , 2002 .

[7]  E. C. Dijkmans,et al.  A 3/5 V compatible I/O buffer , 1995 .

[8]  J. R. Shih,et al.  The failure mechanism of high voltage tolerance IO buffer under ESD , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[9]  Ming-Dou Ker,et al.  ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit , 2005, IEEE Trans. Circuits Syst. I Regul. Pap..

[10]  M. Ker.  Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI , 1999 .

[11]  Steven H. Voldman,et al.  Mixed-voltage interface ESD protection circuits for advanced microprocessors in shallow trench and LOCOS isolation CMOS technologies , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[12]  K.-H. Lin,et al.  On-chip ESD protection design with substrate-triggered technique for mixed-Voltage I/O circuits in subquarter-micrometer CMOS Process , 2004, IEEE Transactions on Electron Devices.

[13]  Tung-Yang Chen,et al.  Substrate-triggered technique for on-chip ESD protection design in a 0.18-/spl mu/m salicided CMOS process , 2003 .

[14]  J.W. Miller,et al.  Engineering the cascoded NMOS output buffer for maximum V/sub t1/ , 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

[15]  E. Worley,et al.  Sub-micron chip ESD protection schemes which avoid avalanching junctions , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[16]  Ming-Dou Ker,et al.  ESD protection design for IC with power-down-mode operation , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).