Multi-Processor Systems on a Chip (MPSoCs) are suitable platforms for the implementation of complex embedded applications. An MPSoC is composable if the functional and temporal behaviour of each application is independent of the absence or presence of other applications. Composability is required for application design and analysis in isolation, and integration with linear effort. In this paper we propose a composable organisation for the top level of a memory hierarchy. This organisation preserves the short (one cycle) access time desirable for a processor's frequent local accesses and enables the predictability demanded by real-time applications. We partition the local memory in two blocks, one private, for local tile data, and another shared for inter-tile data communication. To avoid application interference, we instantiate one such shared local memory block and an Remote Direct Memory Access (RDMA) for each application running on the processor. We implement this organisation on an MPSoC with two processors on an FPGA. On this platform we execute a composition of applications consisting of a JPEG decoder, and a synthetic application. Our experiments indicate that an application's timing is not affected by the behaviour of another application, thus composability is achieved. Moreover, the utilisation of the RDMA component leads to 45% performance increase on average for a number of workloads covering a large range of communication/computation ratios.
[1]
Kees G. W. Goossens,et al.
Composable Resource Sharing Based on Latency-Rate Servers
,
2009,
2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.
[2]
Kees G. W. Goossens,et al.
CoMPSoC: A template for composable and predictable multi-processor system on chips
,
2009,
TODE.
[3]
Kees G. W. Goossens,et al.
The aethereal network on chip after ten years: Goals, evolution, lessons, and future
,
2010,
Design Automation Conference.
[4]
Hermann Kopetz,et al.
Real-time systems
,
2018,
CSC '73.