New architectures for modulo 2N - 1 adders

Two architectures for parallel-prefix modulo 2n - 1 adders are presented in this paper. For large wordlengths we introduce the sparse modulo 2n - 1 adders that achieve significant reduction of the wiring complexity without imposing any delay penalty. Then, the Ling-carry formulation of modulo 2n - 1 addition is presented. Ling modulo adders save one logic level of implementation and provide high-speed solutions for smaller adder widths, where wiring complexity is small. The performance of the proposed adders has been validated with static CMOS implementations. In all examined cases, the proposed designs achieve significant savings in both area and delay compared to previously published architectures.

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