论文信息 - A 6 ns 1.5 V 4 Mb BiCMOS SRAM

A 6 ns 1.5 V 4 Mb BiCMOS SRAM

Although BiCMOS technology has been used to realize high-speed cache memories, the unscalable 0.8 V Vbe of the bipolar makes it difficult to design 1.5 V BiCMOS circuits including bipolar sense amplifiers. Four circuits in a 0.3 /spl mu/m 4 Mb BiCMOS SRAM overcome this difficulty: (1) boost-BinMOS gates for address decoding, (2) an optimized word-boost for a highly-resistive-load memory cell, (3) a stepped-down CML cascoded bipolar sense amplifier, (4) optimum boost-voltage generator. The SRAM has 6 ns access time at a minimum supply voltage, 1.5 V.

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