12.3 A 48GHz BW 225mW/ch Linear Driver IC with Stacked Current-Reuse Architecture in 65nm CMOS for Beyond-400Gb/s Coherent Optical Transmitters

Digital coherent optical transmission technologies are attracting much attention for constructing large-capacity optical core/metro networks and even data center interconnects. Data rates in the next generation of coherent optical transmission systems are expected to exceed 400Gb/s, for which transceivers that can handle symbol rates over 64GBaud and modulation orders over 16-QAM are necessary. Regarding the transmitter, the Optical Internetworking Forum (OIF) is discussing a 64GBaud-class high-bandwidth coherent driver modulator (HB-CDM), which is a broadband electro-optic (EO) front-end module containing optical modulator drivers and Mach-Zehnder modulators (MZMs) [1]. In addition to operating speed, power consumption is also important because it limits the form factor. It is important to reduce the power consumption of the optical modulator driver - one of the most power-hungry blocks in the transmitter - while maintaining a sufficient bandwidth (BW) and an optimal linear voltage swing to drive the MZMs. The temperature dependence of the RF characteristics is also important for practical use because the transceivers will be operated long term in various environments. Here, we present a 65nm-CMOS linear driver IC in which shunt and series multi-peaking techniques with small-footprint inductors extend the BW, and a stacked current-reuse architecture reduces power consumption with voltage from a single power supply. We compensated for temperature dependence by combining an adjustable bandgap reference (BGR) and resistors with a temperature gradient. The driver is equipped with an on-chip DC block with a bias network at inputs and includes a gain control (GC), emphasis control (EMP), a peak detector (PD), and temperature monitor (TM), all controlled by a serial peripheral interface (SPI). A four-channel driver for dual-polarization (DP) IQ modulation is monolithically integrated on one chip, and is co-packaged with a four-channel InP-based MZM as an HB-CDM. The module successfully demonstrated 64Gbaud DP-32QAM (gross bit rate of 640Gb/s).