Effects of layout and process parameters on device/circuit performance and variability for 10nm node FinFET technology

We studied device and circuit performance and their variability for various design and process parameters using TCAD and an analytical RC model. At the 10nm technology node, σC<sub>para</sub> and στ<sub>pd</sub> became greater while σR<sub>para</sub> and σI<sub>on</sub> diminish due to lower ρ<sub>c</sub>. L<sub>g</sub>, H<sub>fin</sub>, P<sub>f2f</sub>, and P<sub>p2p</sub> were found to be key parameters for mitigating variability. Increasing H<sub>fin</sub> provides a path for further performance and area scaling with similar variability. And achieving lower ρ<sub>c</sub> is the biggest module process challenge.